[PATCH] D102466: [RISCV] Support RVP vectors in the calling convention

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D102466#2770479 <https://reviews.llvm.org/D102466#2770479>, @Jim wrote:

> I did the experiments that vector type arguments have been passed as XLenVT. And it is bitcasted back to vector type before using.
>
>   typedef signed char int8x4_t __attribute((vector_size(4))); 
>   
>   int8x4_t foo1(int8x4_t a, int8x4_t b) { 
>     return a + b;
>   }
>
> And its dag looks like:
>
>   t4: i32,ch = CopyFromReg t0, Register:i32 %1
>   t6: v4i8 = bitcast t4
>   t2: i32,ch = CopyFromReg t0, Register:i32 %0 
>   t5: v4i8 = bitcast t2
>   t7: v4i8 = add t6, t5
>
> It is my mistake. This patch is unneeded. How do you think?  @frasercrmck

Sure, if this XLenVT use-case works better for you then I don't see a point in adding unused code. We can revisit if there's another reason to support vectors directly in IR.


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https://reviews.llvm.org/D102466