[llvm] d07d5c1 - [CodeGen] Add support for widening INSERT_SUBVECTOR operands
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Thu May 20 02:37:11 PDT 2021
Author: David Sherwood
Date: 2021-05-20T10:37:03+01:00
New Revision: d07d5c1b061bf7139e32b954d64259b7fe829953
URL: https://github.com/llvm/llvm-project/commit/d07d5c1b061bf7139e32b954d64259b7fe829953
DIFF: https://github.com/llvm/llvm-project/commit/d07d5c1b061bf7139e32b954d64259b7fe829953.diff
LOG: [CodeGen] Add support for widening INSERT_SUBVECTOR operands
When attempting to return something like a <vscale x 1 x i32>
type from a function we end up trying to widen the vector by
inserting a <vscale x 1 x i32> subvector into an undefined
<vscale x 4 x i32> vector. However, during legalisation we
then attempt to widen the INSERT_SUBVECTOR operands and hit
an error in WidenVectorOperand.
This patch adds a new WidenVecOp_INSERT_SUBVECTOR function
that currently only supports inserting subvectors into undefined
vectors.
Differential Revision: https://reviews.llvm.org/D102501
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/AArch64/sve-insert-vector.ll
llvm/test/CodeGen/AArch64/sve-vector-splat.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index a40dd88870335..e95ca266b875a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -928,6 +928,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
SDValue WidenVecOp_EXTEND(SDNode *N);
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue WidenVecOp_STORE(SDNode* N);
SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index e264b72e7256f..8b84864678fda 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4520,6 +4520,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
+ case ISD::INSERT_SUBVECTOR: Res = WidenVecOp_INSERT_SUBVECTOR(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
case ISD::STORE: Res = WidenVecOp_STORE(N); break;
@@ -4834,6 +4835,24 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
return DAG.getBuildVector(VT, dl, Ops);
}
+SDValue DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(SDNode *N) {
+ SDValue SubVec = N->getOperand(1);
+ SDValue InVec = N->getOperand(0);
+
+ if (getTypeAction(InVec.getValueType()) == TargetLowering::TypeWidenVector)
+ InVec = GetWidenedVector(InVec);
+
+ if (getTypeAction(SubVec.getValueType()) == TargetLowering::TypeWidenVector)
+ SubVec = GetWidenedVector(SubVec);
+
+ if (SubVec.getValueType() == InVec.getValueType() && InVec.isUndef() &&
+ N->getConstantOperandVal(2) == 0)
+ return SubVec;
+
+ report_fatal_error("Don't know how to widen the operands for "
+ "INSERT_SUBVECTOR");
+}
+
SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
diff --git a/llvm/test/CodeGen/AArch64/sve-insert-vector.ll b/llvm/test/CodeGen/AArch64/sve-insert-vector.ll
index a07c2ae32d40c..bd5b81469a6a7 100644
--- a/llvm/test/CodeGen/AArch64/sve-insert-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-insert-vector.ll
@@ -246,6 +246,33 @@ define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %ou
}
+; Insert subvectors that need widening
+
+define <vscale x 4 x i32> @insert_nxv1i32_nxv4i32_undef() nounwind {
+; CHECK-LABEL: insert_nxv1i32_nxv4i32_undef:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z0.s, #1 // =0x1
+; CHECK-NEXT: ret
+entry:
+ %0 = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
+ %subvec = shufflevector <vscale x 1 x i32> %0, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %retval = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32> undef, <vscale x 1 x i32> %subvec, i64 0)
+ ret <vscale x 4 x i32> %retval
+}
+
+define <vscale x 6 x i16> @insert_nxv1i16_nxv6i16_undef() nounwind {
+; CHECK-LABEL: insert_nxv1i16_nxv6i16_undef:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov z0.h, #1 // =0x1
+; CHECK-NEXT: ret
+entry:
+ %0 = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
+ %subvec = shufflevector <vscale x 1 x i16> %0, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+ %retval = call <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16> undef, <vscale x 1 x i16> %subvec, i64 0)
+ ret <vscale x 6 x i16> %retval
+}
+
+
declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
@@ -253,3 +280,5 @@ declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscal
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
+declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv1i32(<vscale x 4 x i32>, <vscale x 1 x i32>, i64)
+declare <vscale x 6 x i16> @llvm.experimental.vector.insert.nxv6i16.nxv1i16(<vscale x 6 x i16>, <vscale x 1 x i16>, i64)
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-splat.ll b/llvm/test/CodeGen/AArch64/sve-vector-splat.ll
index 84f6bd6a45693..a82d58b0b4bbe 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-splat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-splat.ll
@@ -132,6 +132,16 @@ define <vscale x 2 x i32> @sve_splat_2xi32(i32 %val) {
;; Widen/split splats of wide vector types.
+define <vscale x 1 x i32> @sve_splat_1xi32(i32 %val) {
+; CHECK-LABEL: sve_splat_1xi32:
+; CHECK: mov z0.s, w0
+; CHECK-NEXT: ret
+entry:
+ %ins = insertelement <vscale x 1 x i32> undef, i32 %val, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %ins, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ ret <vscale x 1 x i32> %splat
+}
+
define <vscale x 12 x i32> @sve_splat_12xi32(i32 %val) {
; CHECK-LABEL: @sve_splat_12xi32
; CHECK: mov z0.s, w0
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