[llvm] 57ea5d4 - [GlobalISel] Fix div+rem -> divrem combine causing use-def violation.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-05-19T23:13:41-07:00
New Revision: 57ea5d4f48754b9b3470fceb197a56ed938ddc02

URL: https://github.com/llvm/llvm-project/commit/57ea5d4f48754b9b3470fceb197a56ed938ddc02
DIFF: https://github.com/llvm/llvm-project/commit/57ea5d4f48754b9b3470fceb197a56ed938ddc02.diff

LOG: [GlobalISel] Fix div+rem -> divrem combine causing use-def violation.

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 29c3b895c262..07efd9a7cc08 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1027,7 +1027,14 @@ void CombinerHelper::applyCombineDivRem(MachineInstr &MI,
 
   bool IsSigned =
       Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_SREM;
-  Builder.setInstrAndDebugLoc(MI);
+
+  // Check which instruction is first in the block so we don't break def-use
+  // deps by "moving" the instruction incorrectly.
+  if (dominates(MI, *OtherMI))
+    Builder.setInstrAndDebugLoc(MI);
+  else
+    Builder.setInstrAndDebugLoc(*OtherMI);
+
   Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM
                               : TargetOpcode::G_UDIVREM,
                      {DestDivReg, DestRemReg},

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
new file mode 100644
index 000000000000..352f6f1e5750
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-apple-ios  -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+
+# Check that we insert the divrem at the place of the G_UDIV, not the G_UREM.
+---
+name:            divrem_use_before_def
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+body:             |
+  ; CHECK-LABEL: name: divrem_use_before_def
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK:   liveins: $x0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+  ; CHECK:   [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
+  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; CHECK:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+  ; CHECK:   G_BRCOND [[DEF]](s1), %bb.2
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
+  ; CHECK:   [[UDIVREM:%[0-9]+]]:_(s32), [[UDIVREM1:%[0-9]+]]:_ = G_UDIVREM [[DEF1]], [[TRUNC]]
+  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UDIVREM]](s32)
+  ; CHECK:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+  ; CHECK:   [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[C2]]
+  ; CHECK:   [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[FREEZE]], [[C]]
+  ; CHECK:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C1]](s64)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SHL]], [[UDIV]]
+  ; CHECK:   G_STORE [[ADD]](s64), [[COPY]](p0) :: (store 8)
+  ; CHECK: bb.2:
+  bb.1:
+    liveins: $x0
+
+    %0:_(p0) = COPY $x0
+    %1:_(s1) = G_IMPLICIT_DEF
+    %2:_(s64) = G_IMPLICIT_DEF
+    %4:_(s64) = G_CONSTANT i64 0
+    %12:_(s64) = G_CONSTANT i64 32
+    G_BRCOND %1(s1), %bb.3
+    G_BR %bb.2
+
+  bb.2:
+    %3:_(s32) = G_TRUNC %2(s64)
+    %5:_(s32) = G_TRUNC %4(s64)
+    %6:_(s32) = G_UDIV %3, %5
+    %7:_(s64) = G_ZEXT %6(s32)
+    %8:_(s32) = COPY %3(s32)
+    %9:_(s32) = COPY %5(s32)
+    %10:_(s32) = G_UREM %8, %9
+    %11:_(s64) = G_ZEXT %10(s32)
+    %13:_(s64) = nuw G_SHL %11, %12(s64)
+    %14:_(s64) = G_OR %2, %13
+    %15:_(s64) = G_FREEZE %14
+    %16:_(s64) = G_UDIV %15, %4
+    %17:_(s64) = G_SHL %7, %12(s64)
+    %18:_(s64) = G_ADD %17, %16
+    G_STORE %18(s64), %0(p0) :: (store 8)
+
+  bb.3:
+
+...