[PATCH] D102819: [PowerPC] Add fix to partword atomic operations

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM. Of course, please ensure that this fixes the issue when the dependent patch is applied prior to committing this.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11359
   BB = exitMBB;
-  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
+  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::RLWINM), dest)
+      .addReg(SrwDestReg)
----------------
```
// Since the shift amount is not a constant, we need to clear
// the upper bits with a separate RLWINM.
```


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Comment at: llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll:103
+; PWR9-NEXT:  # %bb.2: # %entry
+; PWR9-NEXT:    clrlwi 3, 4, 16
+; PWR9-NEXT:    addis 4, 2, global_int at toc@ha
----------------
Presumably this goes away when https://reviews.llvm.org/D101342 lands? Can you please apply that on top of this patch to make sure? Similarly with line 49.


Repository:
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  https://reviews.llvm.org/D102819/new/

https://reviews.llvm.org/D102819