[PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses

Wed May 19 10:52:03 PDT 2021

craig.topper added a comment.

In D102493#2768973 <https://reviews.llvm.org/D102493#2768973>, @frasercrmck wrote:

> In D102493#2766552 <https://reviews.llvm.org/D102493#2766552>, @efriedma wrote:
>
>> Maybe I'm missing something, but `<16 x i8>` is always aligned, right?  Can you convert a `<4 x i32>` load to a `<16 x i8>` load, and bitcast the result?
>
> I hadn't actually considered that. It should work in theory, but we do currently have a cap on the size of the legal vector types so this wouldn't currently work with something like `<128 x i32>`. We could maybe do it pre-legalization, but I don't know if it'd get legalized right back to the unaligned version. The good news it'd presumably work for scalable vectors too. Do you know of other targets doing this?

Can we add the missing MVT types or cap the vXi32/i64 vectors we support to the same total with as the longest vXi8 type?

> Getting masked intrinsics to work via bitcasts may take a bit of doing though. I suppose you'd need to shuffle the indices and add on extra byte offsets like `<0,1,2,3,0,1,...>`. I don't know if that's safe to do since you may risk overflow.

You would also need to duplicate bits in the mask which isn't straight forward.

> @craig.topper can you see anything I've missed here?

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