[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14571-14572
+
+  if (!VT.isScalableVector())
+    return SDValue();
+
----------------
Is this necessary? I guess the node will only every be used by scalable vectors but there's nothing "scalable only" about the transformation.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14574-14576
+  // splice(pg, op1, undef, ...) -> op1
+  if (all_of(drop_begin(N->ops(), 2),
+             [](const SDValue &Op) { return Op.isUndef(); }))
----------------
Not sure what I'm missing here as I expected this to be just `if (N->getOperand(2).isUndef())`.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17820
+
+  Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2);
+
----------------
Feel free to ignore but the use of `Op` here seems arbitrary.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102498/new/

https://reviews.llvm.org/D102498