[PATCH] D102765: [SelectionDAG] Add stub implementation of ReplaceInsertSubVectorResults

[Joe Ellis via Phabricator via llvm-commits]

joechrisellis created this revision.
joechrisellis added reviewers: peterwaller-arm, DavidTruby, bsmith.
Herald added subscribers: ecnelises, hiraditya.
joechrisellis requested review of this revision.
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This is required to prevent hitting an llvm_unreachable when
ReplaceNodeResults is called on an INSERT_SUBVECTOR node. At the moment,
this implementation simply delegates to common code. It is likely that
in the future we will want to change this, but for now, the stub
implementation is sufficient to prevent crashing.

This patch is part of a wider piece of work to allow INSERT_SUBVECTOR to
be lowered when inserting into a smaller-than-legal scalable type. Any
code examples that hit the bad codepath will hit other crashes further
down the line, so this patch does not include tests. Tests which guard
against the crashing behaviour will be added in a later patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102765

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h


Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1060,6 +1060,9 @@
   void ReplaceExtractSubVectorResults(SDNode *N,
                                       SmallVectorImpl<SDValue> &Results,
                                       SelectionDAG &DAG) const;
+  void ReplaceInsertSubVectorResults(SDNode *N,
+                                     SmallVectorImpl<SDValue> &Results,
+                                     SelectionDAG &DAG) const;
 
   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
 
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16559,6 +16559,13 @@
   Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Half));
 }
 
+void AArch64TargetLowering::ReplaceInsertSubVectorResults(
+    SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
+  // TODO: Currently delegating to common code. This might want changing in the
+  //       future.
+  return;
+}
+
 // Create an even/odd pair of X registers holding integer value V.
 static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) {
   SDLoc dl(V.getNode());
@@ -16718,6 +16725,9 @@
   case ISD::EXTRACT_SUBVECTOR:
     ReplaceExtractSubVectorResults(N, Results, DAG);
     return;
+  case ISD::INSERT_SUBVECTOR:
+    ReplaceInsertSubVectorResults(N, Results, DAG);
+    return;
   case ISD::INTRINSIC_WO_CHAIN: {
     EVT VT = N->getValueType(0);
     assert((VT == MVT::i8 || VT == MVT::i16) &&


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