[llvm] 8c71792 - [X86] Remove copy + paste typos in AtomWriteResPair comment.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-05-19T12:25:28+01:00
New Revision: 8c717920d852795447ab14f5d321719b5fa68c56

URL: https://github.com/llvm/llvm-project/commit/8c717920d852795447ab14f5d321719b5fa68c56
DIFF: https://github.com/llvm/llvm-project/commit/8c717920d852795447ab14f5d321719b5fa68c56.diff

LOG: [X86] Remove copy + paste typos in AtomWriteResPair comment.

Remnants from when the Atom model was copied from the Btver2 model.....

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleAtom.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index 6c6287e44cfb..9a3a4f92c17d 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -48,9 +48,6 @@ def : ReadAdvance<ReadAfterVecYLd, 3>;
 
 def : ReadAdvance<ReadInt2Fpu, 0>;
 
-// Many SchedWrites are defined in pairs with and without a folded load.
-// Instructions with folded loads are usually micro-fused, so they only appear
-// as two micro-ops when dispatched by the schedulers.
 // This multiclass defines the resource usage for variants with and without
 // folded loads.
 multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
@@ -59,14 +56,13 @@ multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
                             int RRLat = 1, int RMLat = 1,
                             list<int> RRRes = [1],
                             list<int> RMRes = [1]> {
-  // Register variant is using a single cycle on ExePort.
+  // Register variant.
   def : WriteRes<SchedRW, RRPorts> {
     let Latency = RRLat;
     let ResourceCycles = RRRes;
   }
 
-  // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
-  // latency.
+  // Memory variant.
   def : WriteRes<SchedRW.Folded, RMPorts> {
     let Latency = RMLat;
     let ResourceCycles = RMRes;