[PATCH] D102738: GlobalISel: Do not change register types in lowerLoad

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, paquette.
Herald added subscribers: kerbowa, hiraditya, kristof.beyls, tpr, rovka, nhaehnle, jvesely.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.

      

For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.


https://reviews.llvm.org/D102738

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102738.346304.patch
Type: text/x-patch
Size: 42385 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210518/201153a8/attachment.bin>