[llvm] 62eec33 - [x86] add FMF propagation test for target-specific intrinsic; NFC

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Tue May 18 14:45:49 PDT 2021


Author: Sanjay Patel
Date: 2021-05-18T17:45:40-04:00
New Revision: 62eec33616a462c5860cd980450d53c632b123e8

URL: https://github.com/llvm/llvm-project/commit/62eec33616a462c5860cd980450d53c632b123e8
DIFF: https://github.com/llvm/llvm-project/commit/62eec33616a462c5860cd980450d53c632b123e8.diff

LOG: [x86] add FMF propagation test for target-specific intrinsic; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/fmf-propagation.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/fmf-propagation.ll b/llvm/test/CodeGen/X86/fmf-propagation.ll
index 22ecdc1cf30b..cd19237670e1 100644
--- a/llvm/test/CodeGen/X86/fmf-propagation.ll
+++ b/llvm/test/CodeGen/X86/fmf-propagation.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc -mtriple=x86_64-unknown-unknown -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck %s
 
 ; This tests the propagation of fast-math-flags from IR instructions to SDNodeFlags.
 
@@ -44,3 +44,15 @@ define float @fmf_setcc_canon(float %x, float %y) {
   %ret = select i1 %cmp, float %x, float %y
   ret float %ret
 }
+
+declare <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i32)
+
+; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_target_intrinsic:'
+; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 TargetConstant:i64<9546>
+; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 TargetConstant:i64<9546>
+
+define <16 x float> @fmf_target_intrinsic(<16 x float> %a, <16 x float> %b, <16 x float> %c) nounwind {
+  %t0 = tail call ninf nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i32 4)
+  %t1 = tail call nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %t0, <16 x float> %b, <16 x float> %c, i32 4)
+  ret <16 x float> %t1
+}


        


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