[PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 18 11:18:08 PDT 2021

Previous message: [PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses
Next message: [PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

efriedma added a comment.

Maybe I'm missing something, but `<16 x i8>` is always aligned, right?  Can you convert a `<4 x i32>` load to a `<16 x i8>` load, and bitcast the result?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102493/new/

https://reviews.llvm.org/D102493

Previous message: [PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses
Next message: [PATCH] D102493: [RISCV] Expand unaligned fixed-length vector memory accesses
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list