[llvm] 99c0f16 - [X86] Use Skylake Server model for x86-64-v4 so we have full instruction coverage

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-05-18T18:06:40+01:00
New Revision: 99c0f16ea406a99d2cfc063ffdd1d5d7a3825277

URL: https://github.com/llvm/llvm-project/commit/99c0f16ea406a99d2cfc063ffdd1d5d7a3825277
DIFF: https://github.com/llvm/llvm-project/commit/99c0f16ea406a99d2cfc063ffdd1d5d7a3825277.diff

LOG: [X86] Use Skylake Server model for x86-64-v4 so we have full instruction coverage

The x86-64-v4 generic cpu arch supports AVX512BW/DQ/CD/VLX which isn't covered by the Haswell model, use the SkylakeServer model instead which is a lot closer to what the arch represents.

Differential Revision: https://reviews.llvm.org/D102553

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 6fe7c2175477..6c5a7e8b24bc 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1437,7 +1437,7 @@ def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Feature
 def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
                 ProcessorFeatures.HSWTuning>;
 // Close to the AVX-512 level implemented by Xeon Scalable Processors.
-def : ProcModel<"x86-64-v4", HaswellModel, ProcessorFeatures.X86_64V4Features,
+def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,
                 ProcessorFeatures.SKXTuning>;
 
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