[llvm] 75ea0ab - [X86] AMD Zen 3: fix MULX modelling - don't forget about WriteIMulH (PR50387)

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2021-05-18T19:58:04+03:00
New Revision: 75ea0abaae4547574aa887650b09b98832384fc5

URL: https://github.com/llvm/llvm-project/commit/75ea0abaae4547574aa887650b09b98832384fc5
DIFF: https://github.com/llvm/llvm-project/commit/75ea0abaae4547574aa887650b09b98832384fc5.diff

LOG: [X86] AMD Zen 3: fix MULX modelling - don't forget about WriteIMulH (PR50387)

Otherwise lack thereof will be caught by a defensive check during
scheduling, and we'll crash.

I've literally never seen this syntax before..

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver3.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index cc0a67c2c287..fae9b1b51ef1 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -618,14 +618,14 @@ def Zn3MULX32rr : SchedWriteRes<[Zn3Multiplier]> {
   let ResourceCycles = [1];
   let NumMicroOps = 2;
 }
-def : InstRW<[Zn3MULX32rr], (instrs MULX32rr)>;
+def : InstRW<[Zn3MULX32rr, WriteIMulH], (instrs MULX32rr)>;
 
 def Zn3MULX32rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
   let ResourceCycles = [1, 1, 2];
   let NumMicroOps = Zn3MULX32rr.NumMicroOps;
 }
-def : InstRW<[Zn3MULX32rm], (instrs MULX32rm)>;
+def : InstRW<[Zn3MULX32rm, WriteIMulH], (instrs MULX32rm)>;
 
 defm : Zn3WriteResIntPair<WriteIMul32Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by immediate.
 defm : Zn3WriteResIntPair<WriteIMul32Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 32-bit multiplication by register.
@@ -636,18 +636,18 @@ def Zn3MULX64rr : SchedWriteRes<[Zn3Multiplier]> {
   let ResourceCycles = [1];
   let NumMicroOps = 2;
 }
-def : InstRW<[Zn3MULX64rr], (instrs MULX64rr)>;
+def : InstRW<[Zn3MULX64rr, WriteIMulH], (instrs MULX64rr)>;
 
 def Zn3MULX64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3Multiplier]> {
   let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
   let ResourceCycles = [1, 1, 2];
   let NumMicroOps = Zn3MULX64rr.NumMicroOps;
 }
-def : InstRW<[Zn3MULX64rm], (instrs MULX64rm)>;
+def : InstRW<[Zn3MULX64rm, WriteIMulH], (instrs MULX64rm)>;
 
 defm : Zn3WriteResIntPair<WriteIMul64Imm, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by immediate.
 defm : Zn3WriteResIntPair<WriteIMul64Reg, [Zn3Multiplier], 3, [1], 1>; // Integer 64-bit multiplication by register.
-defm : Zn3WriteResInt<WriteIMulH, [Zn3Multiplier], 2, [2], 2>;         // Integer multiplication, high part.
+defm : Zn3WriteResInt<WriteIMulH, [], 4, [], 0>;         // Integer multiplication, high part.
 
 defm : Zn3WriteResInt<WriteBSWAP32, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 32-bit Swap.
 defm : Zn3WriteResInt<WriteBSWAP64, [Zn3ALU0123], 1, [1], 1>; // Byte Order (Endianness) 64-bit Swap.