[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat
Bradley Smith via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 18 08:45:47 PDT 2021
bsmith added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17720-17722
+ // Skip the splice for the trivial case of concat with undef
+ if (SrcOp2.isUndef())
+ Op = SrcOp1;
----------------
paulwalker-arm wrote:
> This looks like something that can be extracted into a target specific dag combine (i.e. `SPLICE pg, op1, undef -> op1`) being a common scalable vector transform, and means the lowering code will be simpler. You'll see we do something similar for `AArch64ISD::UZP1`.
I've since noted that I actually need support for more than 2 operands in the undef case (i.e. concat_vectors op, undef, undef, undef). Given that, does it still make sense to move this out into a dag combine for SPLICE?
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102498/new/
https://reviews.llvm.org/D102498
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