[PATCH] D102498: [AArch64][SVE] Improve codegen for fixed length vector concat

[JunMa via Phabricator via llvm-commits]

junparser added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17694
 
+SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(
+    SDValue Op, SelectionDAG &DAG) const {
----------------
bsmith wrote:
> junparser wrote:
> > Can we still use ConcatVector here and then lower it performConcatVectorsCombine or td file?
> This is consistent with how all other fixed length operations are handled. The issue with trying to do this in tablegen, is that we'd have to add patterns for every single <= 2048-bit vector type, which is just going to cause an explosion of patterns.
Still we can keep ConcatVector here, and lowering to SPLICE in performConcatVectorsCombine at later phase. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102498/new/

https://reviews.llvm.org/D102498