[PATCH] D102629: [ARM] Fix inline memcpy trip count sequence

[Malhar via Phabricator via llvm-commits]

malharJ added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:11204
 
-  Register BicDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
-  BuildMI(TpEntry, Dl, TII->get(ARM::t2BICri), BicDestReg)
-      .addUse(AddDestReg, RegState::Kill)
-      .addImm(16)
-      .add(predOps(ARMCC::AL))
-      .addReg(0);
-
-  Register LsrDestReg = MRI.createVirtualRegister(&ARM::GPRlrRegClass);
+  Register LsrDestReg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
   BuildMI(TpEntry, Dl, TII->get(ARM::t2LSRri), LsrDestReg)
----------------
I think this might need to be &ARM::GPRlrRegClass ... 

I recall ARMLowOverheadLoops::IterationCountDCE()  not working for me correctly
when I had used rGPR.

But if the tests work correctly then I guess it's fine leaving it as rGPR.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102629/new/

https://reviews.llvm.org/D102629