[llvm] 3cf7983 - [RISCV][test] Add new tests of or/xor in the zbs extension

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2021-05-18T07:10:17+08:00
New Revision: 3cf7983cbe4aba26487709184a0062a6f59aaa9e

URL: https://github.com/llvm/llvm-project/commit/3cf7983cbe4aba26487709184a0062a6f59aaa9e
DIFF: https://github.com/llvm/llvm-project/commit/3cf7983cbe4aba26487709184a0062a6f59aaa9e.diff

LOG: [RISCV][test] Add new tests of or/xor in the zbs extension

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D102625

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv32zbs.ll
    llvm/test/CodeGen/RISCV/rv64zbs.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll
index c55bc01b3276f..bb48c92276884 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll
@@ -777,6 +777,31 @@ define i32 @xor_i32_96(i32 %a) nounwind {
   ret i32 %xor
 }
 
+define i32 @xor_i32_66901(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_66901:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, 1365
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_66901:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 16
+; RV32IB-NEXT:    addi a1, a1, 1365
+; RV32IB-NEXT:    xor a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_66901:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 16
+; RV32IBS-NEXT:    addi a1, a1, 1365
+; RV32IBS-NEXT:    xor a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 66901
+  ret i32 %xor
+}
+
 define i32 @or_i32_4098(i32 %a) nounwind {
 ; RV32I-LABEL: or_i32_4098:
 ; RV32I:       # %bb.0:
@@ -843,3 +868,28 @@ define i32 @or_i32_96(i32 %a) nounwind {
   %or = or i32 %a, 96
   ret i32 %or
 }
+
+define i32 @or_i32_66901(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_66901:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, 1365
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_66901:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 16
+; RV32IB-NEXT:    addi a1, a1, 1365
+; RV32IB-NEXT:    or a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_66901:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 16
+; RV32IBS-NEXT:    addi a1, a1, 1365
+; RV32IBS-NEXT:    or a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 66901
+  ret i32 %or
+}

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64zbs.ll
index 199dcab0deb0a..4803fe0fbd112 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbs.ll
@@ -1302,6 +1302,31 @@ define i64 @or_i64_large(i64 %a) nounwind {
   ret i64 %or
 }
 
+define i64 @xor_i64_66901(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_66901:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw a1, a1, 1365
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_66901:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 16
+; RV64IB-NEXT:    addiw a1, a1, 1365
+; RV64IB-NEXT:    xor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_66901:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 16
+; RV64IBS-NEXT:    addiw a1, a1, 1365
+; RV64IBS-NEXT:    xor a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 66901
+  ret i64 %xor
+}
+
 define i64 @or_i64_4099(i64 %a) nounwind {
 ; RV64I-LABEL: or_i64_4099:
 ; RV64I:       # %bb.0:
@@ -1345,3 +1370,28 @@ define i64 @or_i64_96(i64 %a) nounwind {
   %or = or i64 %a, 96
   ret i64 %or
 }
+
+define i64 @or_i64_66901(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_66901:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw a1, a1, 1365
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_66901:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 16
+; RV64IB-NEXT:    addiw a1, a1, 1365
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_66901:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 16
+; RV64IBS-NEXT:    addiw a1, a1, 1365
+; RV64IBS-NEXT:    or a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %or = or i64 %a, 66901
+  ret i64 %or
+}