[PATCH] D101938: [RISCV] Initial version of a demand based vsetvli insertion pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:235
+
+    if (PrevVSETVLI && (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
+                        MI.modifiesRegister(RISCV::VTYPE))) {
----------------
frasercrmck wrote:
> Not for this patch but should we make sure calls are marked as clobbering VL/VTYPE? Or is there a reason to keep them separate?
I think any call with a regmask operand probably does appear to clobber VL since the regmask marks non-clobbered registers and not include VL. But I think I wasn't sure all calls would end up with a regmask argument.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101938/new/

https://reviews.llvm.org/D101938