[PATCH] D102622: [AMDGPU] Tweak VOP3_INTERP16 profile

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 17 06:50:20 PDT 2021


foad created this revision.
foad added reviewers: dp, rampitec, arsenm.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Set the output register class based on the output type, instead of
hard-coding VGPR_32. I think this is more correct. It doesn't make any
difference at the moment because we use the same class for 16- and
32-bit results, but it might in future if we make more use of true
16-bit register classes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102622

Files:
  llvm/lib/Target/AMDGPU/VOP3Instructions.td


Index: llvm/lib/Target/AMDGPU/VOP3Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -264,7 +264,7 @@
   let HasOMod = !ne(DstVT.Value, f16.Value);
   let HasHigh = 1;
 
-  let Outs64 = (outs VGPR_32:$vdst);
+  let Outs64 = (outs DstRC.RegClass:$vdst);
   let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
   let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102622.345864.patch
Type: text/x-patch
Size: 510 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210517/5676b49a/attachment.bin>


More information about the llvm-commits mailing list