[PATCH] D102575: [SPARC][MC] Support more relocation types

Jessica Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun May 16 12:36:06 PDT 2021


jrtc27 added a comment.

Is "tail reloc" a standard term for this? Seems like that could be confused with the notion of tail calls...



================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:863
 
+template <unsigned Kind>
+OperandMatchResultTy SparcAsmParser::parseTailRelocSym(OperandVector &Operands) {
----------------
Make this an enum class (and pass it as a string in TableGen rather than an int)


================
Comment at: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:895-896
+      switch (VK) {
+        case SparcMCExpr::VK_Sparc_TLS_IE_LD:
+        case SparcMCExpr::VK_Sparc_TLS_IE_LDX:
+          return true;
----------------
These want to be separate kinds so you can stop people using %tie_ld with ldx


================
Comment at: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp:109
+  // Some instructions have phantom operands that only contribute a fixup entry.
+  unsigned symOpNo = 0;
   switch (MI.getOpcode()) {
----------------
Give it a capital first letter as you're touching the code


================
Comment at: llvm/lib/Target/Sparc/SparcISelLowering.h:51
+
+      LOAD_GDOP, // Load operation w/ gdop relocation.
     };
----------------
Line up with the others?


================
Comment at: llvm/lib/Target/Sparc/SparcInstrInfo.td:1381
                           (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
+  def GDOP_LDrr : F3_1<3, 0b000000,
+                      (outs IntRegs:$dst),
----------------
Doesn't belong under TLS


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102575/new/

https://reviews.llvm.org/D102575



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