[PATCH] D101336: [LLD][BPF] Add bpf support

[Fangrui Song via Phabricator via llvm-commits]

MaskRay added a comment.

Does BPF have a Processor Supplement ABI? I think we really should have raised our bar to allow targets which have defined the ABI.
This was also requested in 2018: https://patchwork.ozlabs.org/project/glibc/patch/20180616214515.10737-1-mark@klomp.org/

I don't understand the `if (config->emachine != EM_BPF && type != target->noneRel)` change as
it feels wrong that "BPF llvm target already wrote the section offset in each relocation instruction"

  0000000000000000 <test2>:
         0:       18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r0 = 0 ll
                  0000000000000000:  R_BPF_64_64  sec3
         2:       95 00 00 00 00 00 00 00 exit

If I drop the special case, I will get

  0000000000000000 <test2>:
         0:       00 00 00 00 00 00 00 00 <unknown>
                  0000000000000000:  R_BPF_64_64  sec3
                  ...
         2:       95 00 00 00 00 00 00 00 exit

Why is this `<unknown>`?

I am also very concerned with potentially other differently interpreted concepts, e.g. the re-defined STV_INTERNAL (https://lists.llvm.org/pipermail/cfe-dev/2021-May/068134.html).
This would potentially diverge from other implementations and add some symbol resolution complexity to the generic code (say, we would have to check STV_INTERNAL in Symbols.cpp just for BPF)



================
Comment at: lld/ELF/Arch/BPF.cpp:56
+  default:
+    return R_ABS;
+  }
----------------
See other getRelExpr implementations. The allowed relocation types must be listed.


================
Comment at: lld/test/ELF/lto/bpf-diff-sec.ll:1
+; REQUIRES: bpf
+; RUN: llvm-as %S/Inputs/bpf-diff-sec-1.ll -o %t1.bc
----------------
The auxiliary file is only used once. Please use split-file


Repository:
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https://reviews.llvm.org/D101336