[llvm] d539357 - [ARM] Extra branch on zero tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun May 16 09:23:06 PDT 2021
Author: David Green
Date: 2021-05-16T17:22:52+01:00
New Revision: d539357e1b8a1b5682912a8ea4da6c0088bb770b
URL: https://github.com/llvm/llvm-project/commit/d539357e1b8a1b5682912a8ea4da6c0088bb770b
DIFF: https://github.com/llvm/llvm-project/commit/d539357e1b8a1b5682912a8ea4da6c0088bb770b.diff
LOG: [ARM] Extra branch on zero tests. NFC
Added:
llvm/test/CodeGen/ARM/branch-on-zero.ll
llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
Modified:
llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/branch-on-zero.ll b/llvm/test/CodeGen/ARM/branch-on-zero.ll
new file mode 100644
index 0000000000000..803aa80b44175
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/branch-on-zero.ll
@@ -0,0 +1,191 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple thumbv6m-none-eabi -o - %s | FileCheck %s --check-prefix=CHECK-V6M
+; RUN: llc -mtriple thumbv7m-none-eabi -o - %s | FileCheck %s --check-prefix=CHECK-V7M
+; RUN: llc -mtriple thumbv8.1m.main-none-eabi -mattr=+mve,+lob -o - %s | FileCheck %s --check-prefix=CHECK-V81M
+; RUN: llc -mtriple armv7a-none-eabi -o - %s | FileCheck %s --check-prefix=CHECK-V7A
+
+define i32 @test_lshr(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
+; CHECK-V6M-LABEL: test_lshr:
+; CHECK-V6M: @ %bb.0: @ %entry
+; CHECK-V6M-NEXT: lsrs r2, r2, #2
+; CHECK-V6M-NEXT: beq .LBB0_2
+; CHECK-V6M-NEXT: .LBB0_1: @ %while.body
+; CHECK-V6M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V6M-NEXT: ldm r1!, {r3}
+; CHECK-V6M-NEXT: lsls r3, r3, #1
+; CHECK-V6M-NEXT: stm r0!, {r3}
+; CHECK-V6M-NEXT: subs r2, r2, #1
+; CHECK-V6M-NEXT: bne .LBB0_1
+; CHECK-V6M-NEXT: .LBB0_2: @ %while.end
+; CHECK-V6M-NEXT: movs r0, #0
+; CHECK-V6M-NEXT: bx lr
+;
+; CHECK-V7M-LABEL: test_lshr:
+; CHECK-V7M: @ %bb.0: @ %entry
+; CHECK-V7M-NEXT: lsrs r2, r2, #2
+; CHECK-V7M-NEXT: beq .LBB0_3
+; CHECK-V7M-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V7M-NEXT: subs r1, #4
+; CHECK-V7M-NEXT: subs r0, #4
+; CHECK-V7M-NEXT: .LBB0_2: @ %while.body
+; CHECK-V7M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V7M-NEXT: ldr r3, [r1, #4]!
+; CHECK-V7M-NEXT: subs r2, #1
+; CHECK-V7M-NEXT: lsl.w r3, r3, #1
+; CHECK-V7M-NEXT: str r3, [r0, #4]!
+; CHECK-V7M-NEXT: bne .LBB0_2
+; CHECK-V7M-NEXT: .LBB0_3: @ %while.end
+; CHECK-V7M-NEXT: movs r0, #0
+; CHECK-V7M-NEXT: bx lr
+;
+; CHECK-V81M-LABEL: test_lshr:
+; CHECK-V81M: @ %bb.0: @ %entry
+; CHECK-V81M-NEXT: .save {r7, lr}
+; CHECK-V81M-NEXT: push {r7, lr}
+; CHECK-V81M-NEXT: lsrs r2, r2, #2
+; CHECK-V81M-NEXT: wls lr, r2, .LBB0_2
+; CHECK-V81M-NEXT: .LBB0_1: @ %while.body
+; CHECK-V81M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V81M-NEXT: ldr r2, [r1], #4
+; CHECK-V81M-NEXT: lsls r2, r2, #1
+; CHECK-V81M-NEXT: str r2, [r0], #4
+; CHECK-V81M-NEXT: le lr, .LBB0_1
+; CHECK-V81M-NEXT: .LBB0_2: @ %while.end
+; CHECK-V81M-NEXT: movs r0, #0
+; CHECK-V81M-NEXT: pop {r7, pc}
+;
+; CHECK-V7A-LABEL: test_lshr:
+; CHECK-V7A: @ %bb.0: @ %entry
+; CHECK-V7A-NEXT: mov r3, #0
+; CHECK-V7A-NEXT: cmp r3, r2, lsr #2
+; CHECK-V7A-NEXT: beq .LBB0_3
+; CHECK-V7A-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V7A-NEXT: lsr r2, r2, #2
+; CHECK-V7A-NEXT: .LBB0_2: @ %while.body
+; CHECK-V7A-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V7A-NEXT: ldr r3, [r1], #4
+; CHECK-V7A-NEXT: subs r2, r2, #1
+; CHECK-V7A-NEXT: lsl r3, r3, #1
+; CHECK-V7A-NEXT: str r3, [r0], #4
+; CHECK-V7A-NEXT: bne .LBB0_2
+; CHECK-V7A-NEXT: .LBB0_3: @ %while.end
+; CHECK-V7A-NEXT: mov r0, #0
+; CHECK-V7A-NEXT: bx lr
+entry:
+ %shr = lshr i32 %n, 2
+ %tobool.not4 = icmp eq i32 %shr, 0
+ br i1 %tobool.not4, label %while.end, label %while.body
+
+while.body: ; preds = %entry, %while.body
+ %c.07 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
+ %x.addr.06 = phi i32* [ %incdec.ptr1, %while.body ], [ %x, %entry ]
+ %y.addr.05 = phi i32* [ %incdec.ptr, %while.body ], [ %y, %entry ]
+ %incdec.ptr = getelementptr inbounds i32, i32* %y.addr.05, i32 1
+ %0 = load i32, i32* %y.addr.05, align 4
+ %mul = shl nsw i32 %0, 1
+ %incdec.ptr1 = getelementptr inbounds i32, i32* %x.addr.06, i32 1
+ store i32 %mul, i32* %x.addr.06, align 4
+ %dec = add nsw i32 %c.07, -1
+ %tobool.not = icmp eq i32 %dec, 0
+ br i1 %tobool.not, label %while.end, label %while.body
+
+while.end: ; preds = %while.body, %entry
+ ret i32 0
+}
+
+define i32 @test_lshr2(i32* nocapture %x, i32* nocapture readonly %y, i32 %n) {
+; CHECK-V6M-LABEL: test_lshr2:
+; CHECK-V6M: @ %bb.0: @ %entry
+; CHECK-V6M-NEXT: cmp r2, #4
+; CHECK-V6M-NEXT: blo .LBB1_3
+; CHECK-V6M-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V6M-NEXT: lsrs r2, r2, #2
+; CHECK-V6M-NEXT: .LBB1_2: @ %while.body
+; CHECK-V6M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V6M-NEXT: ldm r1!, {r3}
+; CHECK-V6M-NEXT: lsls r3, r3, #1
+; CHECK-V6M-NEXT: stm r0!, {r3}
+; CHECK-V6M-NEXT: subs r2, r2, #1
+; CHECK-V6M-NEXT: bne .LBB1_2
+; CHECK-V6M-NEXT: .LBB1_3: @ %while.end
+; CHECK-V6M-NEXT: movs r0, #0
+; CHECK-V6M-NEXT: bx lr
+;
+; CHECK-V7M-LABEL: test_lshr2:
+; CHECK-V7M: @ %bb.0: @ %entry
+; CHECK-V7M-NEXT: cmp r2, #4
+; CHECK-V7M-NEXT: blo .LBB1_3
+; CHECK-V7M-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V7M-NEXT: subs r1, #4
+; CHECK-V7M-NEXT: subs r0, #4
+; CHECK-V7M-NEXT: lsrs r2, r2, #2
+; CHECK-V7M-NEXT: .LBB1_2: @ %while.body
+; CHECK-V7M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V7M-NEXT: ldr r3, [r1, #4]!
+; CHECK-V7M-NEXT: subs r2, #1
+; CHECK-V7M-NEXT: lsl.w r3, r3, #1
+; CHECK-V7M-NEXT: str r3, [r0, #4]!
+; CHECK-V7M-NEXT: bne .LBB1_2
+; CHECK-V7M-NEXT: .LBB1_3: @ %while.end
+; CHECK-V7M-NEXT: movs r0, #0
+; CHECK-V7M-NEXT: bx lr
+;
+; CHECK-V81M-LABEL: test_lshr2:
+; CHECK-V81M: @ %bb.0: @ %entry
+; CHECK-V81M-NEXT: .save {r7, lr}
+; CHECK-V81M-NEXT: push {r7, lr}
+; CHECK-V81M-NEXT: cmp r2, #4
+; CHECK-V81M-NEXT: blo .LBB1_3
+; CHECK-V81M-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V81M-NEXT: lsr.w lr, r2, #2
+; CHECK-V81M-NEXT: .LBB1_2: @ %while.body
+; CHECK-V81M-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V81M-NEXT: ldr r2, [r1], #4
+; CHECK-V81M-NEXT: lsls r2, r2, #1
+; CHECK-V81M-NEXT: str r2, [r0], #4
+; CHECK-V81M-NEXT: le lr, .LBB1_2
+; CHECK-V81M-NEXT: .LBB1_3: @ %while.end
+; CHECK-V81M-NEXT: movs r0, #0
+; CHECK-V81M-NEXT: pop {r7, pc}
+;
+; CHECK-V7A-LABEL: test_lshr2:
+; CHECK-V7A: @ %bb.0: @ %entry
+; CHECK-V7A-NEXT: cmp r2, #4
+; CHECK-V7A-NEXT: blo .LBB1_3
+; CHECK-V7A-NEXT: @ %bb.1: @ %while.body.preheader
+; CHECK-V7A-NEXT: lsr r2, r2, #2
+; CHECK-V7A-NEXT: .LBB1_2: @ %while.body
+; CHECK-V7A-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-V7A-NEXT: ldr r3, [r1], #4
+; CHECK-V7A-NEXT: subs r2, r2, #1
+; CHECK-V7A-NEXT: lsl r3, r3, #1
+; CHECK-V7A-NEXT: str r3, [r0], #4
+; CHECK-V7A-NEXT: bne .LBB1_2
+; CHECK-V7A-NEXT: .LBB1_3: @ %while.end
+; CHECK-V7A-NEXT: mov r0, #0
+; CHECK-V7A-NEXT: bx lr
+entry:
+ %tobool.not4 = icmp ult i32 %n, 4
+ br i1 %tobool.not4, label %while.end, label %while.body.preheader
+
+while.body.preheader: ; preds = %entry
+ %shr = lshr i32 %n, 2
+ br label %while.body
+
+while.body: ; preds = %while.body.preheader, %while.body
+ %c.07 = phi i32 [ %dec, %while.body ], [ %shr, %while.body.preheader ]
+ %x.addr.06 = phi i32* [ %incdec.ptr1, %while.body ], [ %x, %while.body.preheader ]
+ %y.addr.05 = phi i32* [ %incdec.ptr, %while.body ], [ %y, %while.body.preheader ]
+ %incdec.ptr = getelementptr inbounds i32, i32* %y.addr.05, i32 1
+ %0 = load i32, i32* %y.addr.05, align 4
+ %mul = shl nsw i32 %0, 1
+ %incdec.ptr1 = getelementptr inbounds i32, i32* %x.addr.06, i32 1
+ store i32 %mul, i32* %x.addr.06, align 4
+ %dec = add nsw i32 %c.07, -1
+ %tobool.not = icmp eq i32 %dec, 0
+ br i1 %tobool.not, label %while.end, label %while.body
+
+while.end: ; preds = %while.body, %entry
+ ret i32 0
+}
+
diff --git a/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
index bf3a0f803b05e..f1b41cbbbe3cc 100644
--- a/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
+++ b/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
@@ -1,10 +1,25 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv7-none-eabi | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
define i32 @test(i32 %n) nounwind {
; CHECK-LABEL: test:
-; CHECK-NOT: mov
-; CHECK: return
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: cmp r0, #1
+; CHECK-NEXT: it eq
+; CHECK-NEXT: popeq {r4, pc}
+; CHECK-NEXT: .LBB0_1: @ %bb.nph
+; CHECK-NEXT: subs r4, r0, #1
+; CHECK-NEXT: .LBB0_2: @ %bb
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: bl f
+; CHECK-NEXT: bl g
+; CHECK-NEXT: subs r4, #1
+; CHECK-NEXT: bne .LBB0_2
+; CHECK-NEXT: @ %bb.3: @ %return
+; CHECK-NEXT: pop {r4, pc}
entry:
%0 = icmp eq i32 %n, 1 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
@@ -30,15 +45,32 @@ return: ; preds = %bb, %entry
}
define i32 @test_dead_cycle(i32 %n) nounwind {
-; CHECK-LABEL: test_dead_cycle:
-; CHECK: subs
; also check for duplicate induction variables (radar 7645034)
-; CHECK: subs r{{.*}}, #1
-; CHECK-NOT: subs r{{.*}}, #1
-; CHECK: bl
-; CHECK-NOT: mov
-; CHECK: bl
-; CHECK: pop
+; CHECK-LABEL: test_dead_cycle:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: cmp r0, #1
+; CHECK-NEXT: it eq
+; CHECK-NEXT: popeq {r4, pc}
+; CHECK-NEXT: .LBB1_1: @ %bb.nph
+; CHECK-NEXT: subs r4, r0, #1
+; CHECK-NEXT: b .LBB1_3
+; CHECK-NEXT: .LBB1_2: @ %bb2
+; CHECK-NEXT: @ in Loop: Header=BB1_3 Depth=1
+; CHECK-NEXT: subs r4, #1
+; CHECK-NEXT: beq .LBB1_5
+; CHECK-NEXT: .LBB1_3: @ %bb
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: cmp r4, #2
+; CHECK-NEXT: blt .LBB1_2
+; CHECK-NEXT: @ %bb.4: @ %bb1
+; CHECK-NEXT: @ in Loop: Header=BB1_3 Depth=1
+; CHECK-NEXT: bl f
+; CHECK-NEXT: bl g
+; CHECK-NEXT: b .LBB1_2
+; CHECK-NEXT: .LBB1_5: @ %return
+; CHECK-NEXT: pop {r4, pc}
entry:
%0 = icmp eq i32 %n, 1 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
new file mode 100644
index 0000000000000..e73d7ecf41063
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll
@@ -0,0 +1,313 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -codegenprepare < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv8.1m.main-none-eabi"
+
+define i32 @lshr3_then(i32 %a) {
+; CHECK-LABEL: @lshr3_then(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 8
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[A]], 3
+; CHECK-NEXT: ret i32 [[L]]
+;
+entry:
+ %c = icmp ult i32 %a, 8
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = lshr i32 %a, 3
+ ret i32 %l
+}
+
+define i32 @lshr5_else(i32 %a) {
+; CHECK-LABEL: @lshr5_else(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 32
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[A]], 5
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp ult i32 %a, 32
+ br i1 %c, label %then, label %else
+
+then:
+ %l = lshr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @lshr2_entry(i32 %a) {
+; CHECK-LABEL: @lshr2_entry(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[A:%.*]], 1
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], 2
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %l = lshr i32 %a, 1
+ %c = icmp ult i32 %a, 2
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @lshr5mismatch(i32 %a) {
+; CHECK-LABEL: @lshr5mismatch(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 17
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = lshr i32 [[A]], 5
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp ult i32 %a, 17
+ br i1 %c, label %then, label %else
+
+then:
+ %l = lshr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @ashr5_else(i32 %a) {
+; CHECK-LABEL: @ashr5_else(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 32
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = ashr i32 [[A]], 5
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp ult i32 %a, 32
+ br i1 %c, label %then, label %else
+
+then:
+ %l = ashr i32 %a, 5
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @add10_else(i32 %a) {
+; CHECK-LABEL: @add10_else(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], 10
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = add i32 [[A]], 10
+; CHECK-NEXT: ret i32 [[L]]
+;
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = add i32 %a, 10
+ ret i32 %l
+}
+
+define i32 @addm10_then(i32 %a) {
+; CHECK-LABEL: @addm10_then(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], 10
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = add i32 [[A]], -10
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = add i32 %a, -10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @add_missmatch(i32 %a) {
+; CHECK-LABEL: @add_missmatch(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], 10
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = add i32 [[A]], 10
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = add i32 %a, 10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i32 @sub10_else(i32 %a) {
+; CHECK-LABEL: @sub10_else(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], 10
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = sub i32 [[A]], 10
+; CHECK-NEXT: ret i32 [[L]]
+;
+entry:
+ %c = icmp eq i32 %a, 10
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = sub i32 %a, 10
+ ret i32 %l
+}
+
+define i32 @subm10_then(i32 %a) {
+; CHECK-LABEL: @subm10_then(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], -10
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[L:%.*]] = sub i32 [[A]], -10
+; CHECK-NEXT: ret i32 [[L]]
+; CHECK: else:
+; CHECK-NEXT: ret i32 0
+;
+entry:
+ %c = icmp eq i32 %a, -10
+ br i1 %c, label %then, label %else
+
+then:
+ %l = sub i32 %a, -10
+ ret i32 %l
+
+else:
+ ret i32 0
+}
+
+define i64 @lshr64(i64 %a) {
+; CHECK-LABEL: @lshr64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i64 [[A:%.*]], 1099511627776
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i64 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = lshr i64 [[A]], 40
+; CHECK-NEXT: ret i64 [[L]]
+;
+entry:
+ %c = icmp ult i64 %a, 1099511627776
+ br i1 %c, label %then, label %else
+
+then:
+ ret i64 0
+
+else:
+ %l = lshr i64 %a, 40
+ ret i64 %l
+}
+
+define i128 @lshr128(i128 %a) {
+; CHECK-LABEL: @lshr128(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C:%.*]] = icmp ult i128 [[A:%.*]], 36893488147419103232
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: ret i128 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = lshr i128 [[A]], 65
+; CHECK-NEXT: ret i128 [[L]]
+;
+entry:
+ %c = icmp ult i128 %a, 36893488147419103232
+ br i1 %c, label %then, label %else
+
+then:
+ ret i128 0
+
+else:
+ %l = lshr i128 %a, 65
+ ret i128 %l
+}
+
+define i32 @addm1_dom(i32 %a) {
+; CHECK-LABEL: @addm1_dom(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[A:%.*]], 100
+; CHECK-NEXT: br i1 [[C1]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK: if:
+; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A]], -1
+; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE]]
+; CHECK: then:
+; CHECK-NEXT: ret i32 0
+; CHECK: else:
+; CHECK-NEXT: [[L:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: ret i32 [[L]]
+;
+entry:
+ %c1 = icmp eq i32 %a, 100
+ br i1 %c1, label %if, label %else
+
+if:
+ %c = icmp eq i32 %a, -1
+ br i1 %c, label %then, label %else
+
+then:
+ ret i32 0
+
+else:
+ %l = add i32 %a, 1
+ ret i32 %l
+}
+
+declare void @other()
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