[llvm] 73635ad - X86SpeculativeLoadHardeningPass::hardenValueInRegister - assert that we have a i8/i16/i32/i64 sized register. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-05-15T15:13:28+01:00
New Revision: 73635adb86bc51612a55440d8b53d828374c83fc

URL: https://github.com/llvm/llvm-project/commit/73635adb86bc51612a55440d8b53d828374c83fc
DIFF: https://github.com/llvm/llvm-project/commit/73635adb86bc51612a55440d8b53d828374c83fc.diff

LOG: X86SpeculativeLoadHardeningPass::hardenValueInRegister - assert that we have a i8/i16/i32/i64 sized register. NFCI.

Silence static analyzer warning for out-of-range access to the SubRegImms[] array.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index 9acf0b719b03..fcaf7c86128a 100644
--- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1915,8 +1915,9 @@ unsigned X86SpeculativeLoadHardeningPass::hardenValueInRegister(
 
   auto *RC = MRI->getRegClass(Reg);
   int Bytes = TRI->getRegSizeInBits(*RC) / 8;
-
   unsigned StateReg = PS->SSA.GetValueAtEndOfBlock(&MBB);
+  assert((Bytes == 1 || Bytes == 2 || Bytes == 4 || Bytes == 8) &&
+         "Unknown register size");
 
   // FIXME: Need to teach this about 32-bit mode.
   if (Bytes != 8) {