[PATCH] D102521: [RISCV] Optimize SEW=64 shifts by splat on RV32.

[Craig Topper via Phabricator via llvm-commits]

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SEW=64 shifts only uses the log2(64) bits of shift amount. If we're
splatting a 64 bit value in 2 parts, we can avoid splatting the
upper bits and just let the low bits be sign extended. They won't
be read anyway.

For the purposes of SelectionDAG semantics of the generic ISD opcodes,
if hi was non-zero or bit 31 of the low is 1, the shift was already
undefined so it should be ok to replace high with sign extend of low.

In order do be able to find the split i64 value before it becomes
a stack operation, I added a new ISD opcode that will be expanded
to the stack spill in PreprocessISelDAG. This new node is conceptually
similar to BuildPairF64, but I expanded earlier so that we could
go through regular isel to get the right VLSE opcode for the LMUL.
BuildPairF64 is expanded in a CustomInserter.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102521

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

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