[PATCH] D102510: [RISCV] Replace AddiPair ComplexPattern with a PatLeaf.

[Craig Topper via Phabricator via llvm-commits]

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The ComplexPattern is looking for an immediate in a certain range
that has a single use. This can be handled with a PatLeaf since
we aren't matching multiple patterns or checking any complicated
relationships between nodes.

This shrinks the isel table a little bit since tablegen no longer
has to generate patterns with commuted operands. With the PatLeaf,
tablegen can see we're matching an immediate which should always
be on the right hand side of add.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102510

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -343,8 +343,15 @@
                                    N->getValueType(0));
 }]>;
 
-// Check if an addition can be broken to a pair of ADDI.
-def AddiPair : ComplexPattern<XLenVT, 1, "selectAddiPair">;
+// Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
+// in which imm = imm0 + imm1 and both imm0 and imm1 are simm12.
+def AddiPair : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate operand must be in range [-4096,-2049] or [2048,4094].
+  int64_t Imm = N->getSExtValue();
+  return (-4096 <= Imm && Imm <= -2049) || (2048 <= Imm && Imm <= 4094);
+}]>;
 
 // Return imm/2.
 def AddiPairImmA : SDNodeXForm<imm, [{
@@ -1299,14 +1306,14 @@
 def : Pat<(debugtrap), (EBREAK)>;
 
 /// Simple optimization
-def : Pat<(add GPR:$rs1, (AddiPair GPR:$rs2)),
-          (ADDI (ADDI GPR:$rs1, (AddiPairImmB GPR:$rs2)),
+def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
+          (ADDI (ADDI GPR:$rs1, (AddiPairImmB AddiPair:$rs2)),
                 (AddiPairImmA GPR:$rs2))>;
 
 let Predicates = [IsRV64] in {
-def : Pat<(sext_inreg (add_oneuse GPR:$rs1, (AddiPair GPR:$rs2)), i32),
-          (ADDIW (ADDIW GPR:$rs1, (AddiPairImmB GPR:$rs2)),
-                 (AddiPairImmA GPR:$rs2))>;
+def : Pat<(sext_inreg (add_oneuse GPR:$rs1, (AddiPair:$rs2)), i32),
+          (ADDIW (ADDIW GPR:$rs1, (AddiPairImmB AddiPair:$rs2)),
+                 (AddiPairImmA AddiPair:$rs2))>;
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -57,8 +57,6 @@
   bool selectSExti32(SDValue N, SDValue &Val);
   bool selectZExti32(SDValue N, SDValue &Val);
 
-  bool selectAddiPair(SDValue N, SDValue &Val);
-
   bool MatchSLLIUW(SDNode *N) const;
 
   bool selectVLOp(SDValue N, SDValue &VL);
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1287,23 +1287,6 @@
   return false;
 }
 
-// Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
-// in which imm = imm0 + imm1 and both imm0 and imm1 are simm12.
-bool RISCVDAGToDAGISel::selectAddiPair(SDValue N, SDValue &Val) {
-  if (auto *ConstOp = dyn_cast<ConstantSDNode>(N)) {
-    // The immediate operand must have only use.
-    if (!(ConstOp->hasOneUse()))
-      return false;
-    // The immediate operand must be in range [-4096,-2049] or [2048,4094].
-    int64_t Imm = ConstOp->getSExtValue();
-    if ((-4096 <= Imm && Imm <= -2049) || (2048 <= Imm && Imm <= 4094)) {
-      Val = N;
-      return true;
-    }
-  }
-  return false;
-}
-
 // Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
 // on RV64).
 // SLLIUW is the same as SLLI except for the fact that it clears the bits


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