[llvm] 11b34e7 - [ARM] Define CPSR on MEMCPY pseudos

[David Green via llvm-commits]

Author: David Green
Date: 2021-05-14T15:06:59+01:00
New Revision: 11b34e78c1e2fd5e7cec224d99400216334e2893

URL: https://github.com/llvm/llvm-project/commit/11b34e78c1e2fd5e7cec224d99400216334e2893
DIFF: https://github.com/llvm/llvm-project/commit/11b34e78c1e2fd5e7cec224d99400216334e2893.diff

LOG: [ARM] Define CPSR on MEMCPY pseudos

These pseudos are converted post-isel into t2WhileLoopStart and
t2LoopEnd/LoopDec instructions, which themselves are defined to clobber
CPSR. Doing the same with the MEMCPY nodes will make sure they are
scheduled correctly to not end up with incorrect uses.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMISelLowering.cpp
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/test/CodeGen/Thumb2/mve-tp-loop.ll
    llvm/test/CodeGen/Thumb2/mve-tp-loop.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index f9f0b57f4668e..2552d446749cc 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -11319,7 +11319,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     // 1) A terminator(t2WhileLoopStart) will be placed at that site.
     // 2) Since a TPLoopBody will be added later, any phis in successive blocks
     //    need to be updated. splitAt() already handles this.
-    TpExit = BB->splitAt(MI);
+    TpExit = BB->splitAt(MI, false);
     if (TpExit == BB) {
       assert(BB->canFallThrough() && "Exit Block must be Fallthrough of the "
                                      "block containing memcpy/memset Pseudo");
@@ -11327,7 +11327,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
       BuildMI(BB, dl, TII->get(ARM::t2B))
           .addMBB(TpExit)
           .add(predOps(ARMCC::AL));
-      TpExit = BB->splitAt(MI);
+      TpExit = BB->splitAt(MI, false);
     }
 
     // Add logic for iteration count

diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index d7c034800b2be..86431919faff5 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -6870,7 +6870,7 @@ def SDT_MVEMEMCPYLOOPNODE
 def MVE_MEMCPYLOOPNODE : SDNode<"ARMISD::MEMCPYLOOP", SDT_MVEMEMCPYLOOPNODE,
                                 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
 
-let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
+let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CPSR] in {
   def MVE_MEMCPYLOOPINST : PseudoInst<(outs),
         (ins rGPR:$dst, rGPR:$src, rGPR:$sz),
         NoItinerary,
@@ -6882,7 +6882,7 @@ def SDT_MVEMEMSETLOOPNODE
 def MVE_MEMSETLOOPNODE : SDNode<"ARMISD::MEMSETLOOP", SDT_MVEMEMSETLOOPNODE,
                                 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
 
-let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
+let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CPSR] in {
   def MVE_MEMSETLOOPINST : PseudoInst<(outs),
         (ins rGPR:$dst, MQPR:$src, rGPR:$sz),
         NoItinerary,

diff  --git a/llvm/test/CodeGen/Thumb2/mve-tp-loop.ll b/llvm/test/CodeGen/Thumb2/mve-tp-loop.ll
index 6eb1338eaf25d..f19a6126b8009 100644
--- a/llvm/test/CodeGen/Thumb2/mve-tp-loop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-tp-loop.ll
@@ -409,5 +409,39 @@ entry:
   ret void
 }
 
+define void @csprlive(i32* noalias %X, i32* noalias readonly %Y, i32 %n) {
+; CHECK-LABEL: csprlive:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r7, lr}
+; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    wlstp.8 lr, r2, .LBB16_2
+; CHECK-NEXT:  .LBB16_1: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vldrb.u8 q0, [r1], #16
+; CHECK-NEXT:    vstrb.8 q0, [r0], #16
+; CHECK-NEXT:    letp lr, .LBB16_1
+; CHECK-NEXT:  .LBB16_2: @ %entry
+; CHECK-NEXT:    bl other
+; CHECK-NEXT:    pop {r7, pc}
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  %X.bits = bitcast i32* %X to i8*
+  %Y.bits = bitcast i32* %Y to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %X.bits, i8* align 4 %Y.bits, i32 %n, i1 false)
+  br i1 %cmp6, label %if, label %else
+
+if:
+  call void @other()
+  br label %cleanup
+
+else:
+  call void @other()
+  br label %cleanup
+
+cleanup:
+  ret void
+}
+
+declare void @other()
+
 attributes #0 = { noinline  optnone }
 attributes #1 = { optsize }

diff  --git a/llvm/test/CodeGen/Thumb2/mve-tp-loop.mir b/llvm/test/CodeGen/Thumb2/mve-tp-loop.mir
index e652846197ab5..fa9a05a353e4e 100644
--- a/llvm/test/CodeGen/Thumb2/mve-tp-loop.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-tp-loop.mir
@@ -88,7 +88,7 @@ body:             |
     %2:rgpr = COPY $r2
     %1:rgpr = COPY $r1
     %0:rgpr = COPY $r0
-    MVE_MEMCPYLOOPINST %0, %1, %2
+    MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr
     tBX_RET 14 /* CC::al */, $noreg
 
 ...
@@ -142,7 +142,7 @@ body:             |
   bb.1.for.body.preheader:
     successors: %bb.2(0x80000000)
 
-    MVE_MEMCPYLOOPINST %0, %1, %2
+    MVE_MEMCPYLOOPINST %0, %1, %2, implicit-def $cpsr
 
   bb.2.for.cond.cleanup:
     tBX_RET 14 /* CC::al */, $noreg
@@ -180,7 +180,7 @@ body:             |
     %2:rgpr = COPY $r2
     %1:mqpr = COPY $r1
     %0:rgpr = COPY $r0
-    MVE_MEMSETLOOPINST %0, %1, %2
+    MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr
     tBX_RET 14 /* CC::al */, $noreg
 
 ...
@@ -231,7 +231,7 @@ body:             |
     t2B %bb.1, 14 /* CC::al */, $noreg
 
   bb.1.for.body.preheader:
-    MVE_MEMSETLOOPINST %0, %1, %2
+    MVE_MEMSETLOOPINST %0, %1, %2, implicit-def $cpsr
 
   bb.2.for.cond.cleanup:
     tBX_RET 14 /* CC::al */, $noreg