[llvm] b41e130 - [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().

[Hsiangkai Wang via llvm-commits]

Author: Hsiangkai Wang
Date: 2021-05-14T21:31:06+08:00
New Revision: b41e1306b80f20a857f0e285e51ea453eb7888a1

URL: https://github.com/llvm/llvm-project/commit/b41e1306b80f20a857f0e285e51ea453eb7888a1
DIFF: https://github.com/llvm/llvm-project/commit/b41e1306b80f20a857f0e285e51ea453eb7888a1.diff

LOG: [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().

The MachineBasicBlock::iterator is continuously changing during
generating the frame handling instructions. We should use the DebugLoc
from the caller, instead of getting it from the changing iterator.

If the prologue instructions located in a basic block without any other
instructions after these prologue instructions, the iterator will be
updated to the boundary of the basic block and it is invalid to use the
iterator to access DebugLoc. This patch also fixes the crash when
accessing DebugLoc using the iterator.

Differential Revision: https://reviews.llvm.org/D102386

Added: 
    llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.h
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f1fd9212fb334..2417daf5fb4e1 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -319,7 +319,8 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
   }
 
   // 1. Multiply the number of v-slots to the length of registers
-  Register FactorRegister = TII->getVLENFactoredAmount(MF, MBB, MBBI, Amount);
+  Register FactorRegister =
+      TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount);
   // 2. SP = SP - RVV stack size
   BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
       .addReg(SPReg)

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 335980e4579e5..ba99765cd8eae 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1356,6 +1356,7 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
                                                MachineBasicBlock &MBB,
                                                MachineBasicBlock::iterator II,
+                                               const DebugLoc &DL,
                                                int64_t Amount) const {
   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
   assert(Amount % 8 == 0 &&
@@ -1363,7 +1364,6 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
-  DebugLoc DL = II->getDebugLoc();
   int64_t NumOfVReg = Amount / 8;
 
   Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index ae03d121f42df..2f401f1c0791c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -145,7 +145,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator II,
-                                 int64_t Amount) const;
+                                 const DebugLoc &DL, int64_t Amount) const;
 
   Optional<std::pair<unsigned, unsigned>>
   isRVVSpillForZvlsseg(unsigned Opcode) const;

diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 730e9992d7c16..426628bd3f721 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -228,7 +228,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     }
     // 1. Get vlenb && multiply vlen with the number of vector registers.
     ScalableFactorRegister =
-        TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
+        TII->getVLENFactoredAmount(MF, MBB, II, DL, ScalableValue);
   }
 
   if (!isInt<12>(Offset.getFixed())) {

diff  --git a/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
new file mode 100644
index 0000000000000..36db7651afb09
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -o - %s \
+# RUN:   -stop-after=prologepilog | FileCheck %s
+
+--- |
+  define void @foo() !dbg !0 {
+  entry:
+    %va = alloca <vscale x 2 x i32>, align 4, !dbg !1
+    br label %end
+  end:
+    ret void, !dbg !2
+  }
+
+  !0 = distinct !DISubprogram(name: "foo", line: 3, scopeLine: 3)
+  !1 = !DILocation(line: 4, column: 14, scope: !0)
+  !2 = !DILocation(line: 5, column: 3, scope: !0)
+
+...
+---
+name: foo
+tracksRegLiveness: true
+stack:
+  - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 }
+body: |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   $x2 = frame-setup ADDI $x2, -16
+  ; CHECK:   CFI_INSTRUCTION def_cfa_offset 16
+  ; CHECK:   $x10 = PseudoReadVLENB
+  ; CHECK:   $x10 = SLLI killed $x10, 1
+  ; CHECK:   $x2 = SUB $x2, killed $x10
+  ; CHECK: bb.1:
+  ; CHECK:   $x10 = PseudoReadVLENB
+  ; CHECK:   $x10 = SLLI killed $x10, 1
+  ; CHECK:   $x2 = ADD $x2, killed $x10
+  ; CHECK:   $x2 = frame-destroy ADDI $x2, 16
+  ; CHECK:   PseudoRET
+  bb.0:
+  bb.1:
+    PseudoRET