[llvm] 434b278 - [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri May 14 06:13:56 PDT 2021
Author: Dmitry Preobrazhensky
Date: 2021-05-14T16:13:30+03:00
New Revision: 434b278cde81800eb23a0496d9f6abdbc30e15bc
URL: https://github.com/llvm/llvm-project/commit/434b278cde81800eb23a0496d9f6abdbc30e15bc
DIFF: https://github.com/llvm/llvm-project/commit/434b278cde81800eb23a0496d9f6abdbc30e15bc.diff
LOG: [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX90A;
- minor bugfixing and improvements.
Added:
llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst
llvm/docs/AMDGPU/gfx90a_dst.rst
llvm/docs/AMDGPU/gfx90a_fx_operand.rst
llvm/docs/AMDGPU/gfx90a_hwreg.rst
llvm/docs/AMDGPU/gfx90a_imask.rst
llvm/docs/AMDGPU/gfx90a_imm16.rst
llvm/docs/AMDGPU/gfx90a_imm16_1.rst
llvm/docs/AMDGPU/gfx90a_imm16_2.rst
llvm/docs/AMDGPU/gfx90a_label.rst
llvm/docs/AMDGPU/gfx90a_m.rst
llvm/docs/AMDGPU/gfx90a_m_1.rst
llvm/docs/AMDGPU/gfx90a_msg.rst
llvm/docs/AMDGPU/gfx90a_opt.rst
llvm/docs/AMDGPU/gfx90a_probe.rst
llvm/docs/AMDGPU/gfx90a_saddr.rst
llvm/docs/AMDGPU/gfx90a_saddr_1.rst
llvm/docs/AMDGPU/gfx90a_sbase.rst
llvm/docs/AMDGPU/gfx90a_sbase_1.rst
llvm/docs/AMDGPU/gfx90a_sbase_2.rst
llvm/docs/AMDGPU/gfx90a_sdata.rst
llvm/docs/AMDGPU/gfx90a_sdata_1.rst
llvm/docs/AMDGPU/gfx90a_sdata_2.rst
llvm/docs/AMDGPU/gfx90a_sdata_3.rst
llvm/docs/AMDGPU/gfx90a_sdata_4.rst
llvm/docs/AMDGPU/gfx90a_sdata_5.rst
llvm/docs/AMDGPU/gfx90a_sdst.rst
llvm/docs/AMDGPU/gfx90a_sdst_1.rst
llvm/docs/AMDGPU/gfx90a_sdst_2.rst
llvm/docs/AMDGPU/gfx90a_sdst_3.rst
llvm/docs/AMDGPU/gfx90a_sdst_4.rst
llvm/docs/AMDGPU/gfx90a_sdst_5.rst
llvm/docs/AMDGPU/gfx90a_sdst_6.rst
llvm/docs/AMDGPU/gfx90a_sdst_7.rst
llvm/docs/AMDGPU/gfx90a_simm32.rst
llvm/docs/AMDGPU/gfx90a_simm32_1.rst
llvm/docs/AMDGPU/gfx90a_simm32_2.rst
llvm/docs/AMDGPU/gfx90a_soffset.rst
llvm/docs/AMDGPU/gfx90a_soffset_1.rst
llvm/docs/AMDGPU/gfx90a_soffset_2.rst
llvm/docs/AMDGPU/gfx90a_src.rst
llvm/docs/AMDGPU/gfx90a_src_1.rst
llvm/docs/AMDGPU/gfx90a_src_10.rst
llvm/docs/AMDGPU/gfx90a_src_11.rst
llvm/docs/AMDGPU/gfx90a_src_2.rst
llvm/docs/AMDGPU/gfx90a_src_3.rst
llvm/docs/AMDGPU/gfx90a_src_4.rst
llvm/docs/AMDGPU/gfx90a_src_5.rst
llvm/docs/AMDGPU/gfx90a_src_6.rst
llvm/docs/AMDGPU/gfx90a_src_7.rst
llvm/docs/AMDGPU/gfx90a_src_8.rst
llvm/docs/AMDGPU/gfx90a_src_9.rst
llvm/docs/AMDGPU/gfx90a_srsrc.rst
llvm/docs/AMDGPU/gfx90a_srsrc_1.rst
llvm/docs/AMDGPU/gfx90a_ssamp.rst
llvm/docs/AMDGPU/gfx90a_ssrc.rst
llvm/docs/AMDGPU/gfx90a_ssrc_1.rst
llvm/docs/AMDGPU/gfx90a_ssrc_2.rst
llvm/docs/AMDGPU/gfx90a_ssrc_3.rst
llvm/docs/AMDGPU/gfx90a_ssrc_4.rst
llvm/docs/AMDGPU/gfx90a_ssrc_5.rst
llvm/docs/AMDGPU/gfx90a_ssrc_6.rst
llvm/docs/AMDGPU/gfx90a_ssrc_7.rst
llvm/docs/AMDGPU/gfx90a_ssrc_8.rst
llvm/docs/AMDGPU/gfx90a_type_deviation.rst
llvm/docs/AMDGPU/gfx90a_vaddr.rst
llvm/docs/AMDGPU/gfx90a_vaddr_1.rst
llvm/docs/AMDGPU/gfx90a_vaddr_2.rst
llvm/docs/AMDGPU/gfx90a_vaddr_3.rst
llvm/docs/AMDGPU/gfx90a_vaddr_4.rst
llvm/docs/AMDGPU/gfx90a_vaddr_5.rst
llvm/docs/AMDGPU/gfx90a_vcc.rst
llvm/docs/AMDGPU/gfx90a_vdata.rst
llvm/docs/AMDGPU/gfx90a_vdata0.rst
llvm/docs/AMDGPU/gfx90a_vdata0_1.rst
llvm/docs/AMDGPU/gfx90a_vdata1.rst
llvm/docs/AMDGPU/gfx90a_vdata1_1.rst
llvm/docs/AMDGPU/gfx90a_vdata_1.rst
llvm/docs/AMDGPU/gfx90a_vdata_10.rst
llvm/docs/AMDGPU/gfx90a_vdata_2.rst
llvm/docs/AMDGPU/gfx90a_vdata_3.rst
llvm/docs/AMDGPU/gfx90a_vdata_4.rst
llvm/docs/AMDGPU/gfx90a_vdata_5.rst
llvm/docs/AMDGPU/gfx90a_vdata_6.rst
llvm/docs/AMDGPU/gfx90a_vdata_7.rst
llvm/docs/AMDGPU/gfx90a_vdata_8.rst
llvm/docs/AMDGPU/gfx90a_vdata_9.rst
llvm/docs/AMDGPU/gfx90a_vdst.rst
llvm/docs/AMDGPU/gfx90a_vdst_1.rst
llvm/docs/AMDGPU/gfx90a_vdst_10.rst
llvm/docs/AMDGPU/gfx90a_vdst_11.rst
llvm/docs/AMDGPU/gfx90a_vdst_12.rst
llvm/docs/AMDGPU/gfx90a_vdst_13.rst
llvm/docs/AMDGPU/gfx90a_vdst_14.rst
llvm/docs/AMDGPU/gfx90a_vdst_15.rst
llvm/docs/AMDGPU/gfx90a_vdst_16.rst
llvm/docs/AMDGPU/gfx90a_vdst_17.rst
llvm/docs/AMDGPU/gfx90a_vdst_18.rst
llvm/docs/AMDGPU/gfx90a_vdst_19.rst
llvm/docs/AMDGPU/gfx90a_vdst_2.rst
llvm/docs/AMDGPU/gfx90a_vdst_3.rst
llvm/docs/AMDGPU/gfx90a_vdst_4.rst
llvm/docs/AMDGPU/gfx90a_vdst_5.rst
llvm/docs/AMDGPU/gfx90a_vdst_6.rst
llvm/docs/AMDGPU/gfx90a_vdst_7.rst
llvm/docs/AMDGPU/gfx90a_vdst_8.rst
llvm/docs/AMDGPU/gfx90a_vdst_9.rst
llvm/docs/AMDGPU/gfx90a_vsrc.rst
llvm/docs/AMDGPU/gfx90a_vsrc_1.rst
llvm/docs/AMDGPU/gfx90a_vsrc_2.rst
llvm/docs/AMDGPU/gfx90a_vsrc_3.rst
llvm/docs/AMDGPU/gfx90a_vsrc_4.rst
llvm/docs/AMDGPU/gfx90a_vsrc_5.rst
llvm/docs/AMDGPU/gfx90a_waitcnt.rst
Modified:
llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
llvm/docs/AMDGPUModifierSyntax.rst
llvm/docs/AMDGPUOperandSyntax.rst
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst
new file mode 100644
index 0000000000000..14fb9a46b7445
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst
@@ -0,0 +1,2103 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of gfx90a Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of gfx90a instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_f64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx90a_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx90a_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx90a_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata0<amdgpu_synid_gfx90a_vdata0_1>`, :ref:`vdata1<amdgpu_synid_gfx90a_vdata1_1>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx90a_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_1>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx90a_vdst_4>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_5>`::ref:`opt<amdgpu_synid_gfx90a_opt>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx90a_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_short :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx90a_vdst_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx90a_vdst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx90a_vdata_5>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx90a_vdata_4>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid_gfx90a_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load :ref:`vdst<amdgpu_synid_gfx90a_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid_gfx90a_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx90a_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx90a_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck :ref:`vdst<amdgpu_synid_gfx90a_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx90a_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample :ref:`vdst<amdgpu_synid_gfx90a_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx90a_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid_gfx90a_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx90a_vdata_6>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx90a_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx90a_vdata_7>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MTBUF
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx90a_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx90a_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_f32 :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_f64 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_10>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_max_f64 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_min_f64 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_pk_add_f16 :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx90a_vdata_8>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_9>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_invl2
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx90a_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_hi_x :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx90a_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx90a_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx90a_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx90a_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx90a_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx90a_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx90a_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx90a_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_lds_dword :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx90a_vdata>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx90a_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_wbinvl1
+ buffer_wbinvl1_vol
+ buffer_wbl2
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`probe<amdgpu_synid_gfx90a_probe>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>`
+ s_atc_probe_buffer :ref:`probe<amdgpu_synid_gfx90a_probe>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_2>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_2>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`b64x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx90a_sdata>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_1>`::ref:`dst<amdgpu_synid_gfx90a_dst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx90a_sdst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx90a_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx90a_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx90a_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx90a_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_1>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_2>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>`
+ s_dcache_inv
+ s_dcache_inv_vol
+ s_dcache_wb
+ s_dcache_wb_vol
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx90a_sdst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_1>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx90a_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx90a_sdst_4>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`
+ s_memtime :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid_gfx90a_sdst>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx90a_sdst_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx90a_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx90a_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase_2>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx90a_sdata_3>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx90a_sdata_4>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx90a_sdata_5>`, :ref:`sbase<amdgpu_synid_gfx90a_sbase>`, :ref:`soffset<amdgpu_synid_gfx90a_soffset_1>` :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_cbranch_join :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_2>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_2>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_3>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_3>`
+ s_set_gpr_idx_idx :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_3>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_3>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_1>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_4>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_4>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_1>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+ s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid_gfx90a_ssrc>`, :ref:`imask<amdgpu_synid_gfx90a_imask>`
+ s_setvskip :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_i_fork :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_5>`, :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16_1>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`hwreg<amdgpu_synid_gfx90a_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_5>`, :ref:`imm16<amdgpu_synid_gfx90a_imm16>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx90a_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx90a_ssrc_6>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx90a_hwreg>`, :ref:`simm32<amdgpu_synid_gfx90a_simm32>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid_gfx90a_label>`
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_sendmsg :ref:`msg<amdgpu_synid_gfx90a_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid_gfx90a_msg>`
+ s_set_gpr_idx_mode :ref:`imask<amdgpu_synid_gfx90a_imask>`
+ s_set_gpr_idx_off
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx90a_imm16_2>`
+ s_ttracedata
+ s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx90a_waitcnt>`
+ s_wakeup
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_mov_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_13>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc>`
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_ceil_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_3>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_3>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_cvt_f32_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_cvt_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_cvt_u32_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_exp_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_exp_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_floor_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_fract_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_frexp_exp_i32_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_frexp_mant_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_log_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_log_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_7>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_screen_partition_4se_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_screen_partition_4se_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_2>`
+ v_trunc_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_add_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_add_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_add_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`
+ v_addc_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_addc_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_ashrrev_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`
+ v_dot2c_i32_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>`
+ v_dot8c_i32_i4_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_fmac_f64_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp64_ctrl<amdgpu_synid_dpp64_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i16<amdgpu_synid_gfx90a_type_deviation>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`i16<amdgpu_synid_gfx90a_type_deviation>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`i16<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_lshlrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_lshrrev_b16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mac_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mac_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_madak_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`simm32<amdgpu_synid_gfx90a_simm32_1>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`simm32<amdgpu_synid_gfx90a_simm32_2>`
+ v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`simm32<amdgpu_synid_gfx90a_simm32_1>`, :ref:`vsrc2<amdgpu_synid_gfx90a_vsrc_1>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`simm32<amdgpu_synid_gfx90a_simm32_2>`, :ref:`vsrc2<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_i16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_lo_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_lo_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_sub_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_sub_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`
+ v_subb_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subb_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`
+ v_subbrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_subrev_co_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_co_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_subrev_u16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_subrev_u32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_subrev_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>` :ref:`dpp32_ctrl<amdgpu_synid_dpp32_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_add_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_add_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_addc_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx90a_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_ashrrev_i16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_f_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_t_u16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_cmpx_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx90a_ssrc_3>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_legacy_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`i16<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_lshlrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_lshrrev_b16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`
+ v_mac_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`i64<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_legacy_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`u64<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_max_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_min_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_16>`::ref:`b128<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx90a_vsrc_3>`::ref:`b128<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`b64<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx90a_sdst_7>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_1>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_7>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subb_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx90a_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subbrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`ssrc2<amdgpu_synid_gfx90a_ssrc_3>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_u16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_u32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`, :ref:`src<amdgpu_synid_gfx90a_src_5>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`ssrc0<amdgpu_synid_gfx90a_ssrc_8>`, :ref:`ssrc1<amdgpu_synid_gfx90a_ssrc_7>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`
+
+VOP3P
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_read_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`vsrc<amdgpu_synid_gfx90a_vsrc>`
+ v_accvgpr_write_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_13>`, :ref:`src<amdgpu_synid_gfx90a_src_6>`
+ v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`f16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`i16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`i4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`i32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`u4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`u4x8<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`u32<amdgpu_synid_gfx90a_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`::ref:`fx<amdgpu_synid_gfx90a_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mfma_f32_16x16x16bf16_1k :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x16f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x1f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x2bf16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4bf16_1k :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x4f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_16x16x8bf16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x1f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_18>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_9>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x2bf16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_18>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_9>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x2f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4bf16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4bf16_1k :ref:`vdst<amdgpu_synid_gfx90a_vdst_18>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_9>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x4f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_18>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_9>`::ref:`f32x32<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8bf16_1k :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_32x32x8f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`f32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x1f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`f32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x2bf16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`bf16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4bf16_1k :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`bf16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f32_4x4x4f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f16x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`f32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f64_16x16x4f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_19>`::ref:`f64x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_10>`::ref:`f64x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_f64_4x4x4f64 :ref:`vdst<amdgpu_synid_gfx90a_vdst_1>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_4>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_11>`::ref:`f64<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_16x16x16i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`i32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`i32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_16x16x4i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`i32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`i32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x4i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_18>`::ref:`i32x32<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_9>`::ref:`i32x32<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_32x32x8i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_17>`::ref:`i32x16<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_8>`::ref:`i32x16<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_mfma_i32_4x4x4i8 :ref:`vdst<amdgpu_synid_gfx90a_vdst_2>`::ref:`i32x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_5>`::ref:`i8x4<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_7>`::ref:`i32x4<amdgpu_synid_gfx90a_type_deviation>` :ref:`cbsz<amdgpu_synid_cbsz>` :ref:`abid<amdgpu_synid_abid>` :ref:`blgp<amdgpu_synid_blgp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`, :ref:`src2<amdgpu_synid_gfx90a_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_fma_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src2<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`u16x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`, :ref:`src2<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mov_b32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`b32x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_15>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src0<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>`, :ref:`src1<amdgpu_synid_gfx90a_src_5>`::ref:`f32x2<amdgpu_synid_gfx90a_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_f_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_f_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_t_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_t_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_2>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_class_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`::ref:`b32<amdgpu_synid_gfx90a_type_deviation>`
+ v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_f_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_f_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_f_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_le_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_le_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_le_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_o_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_t_i16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_t_i16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_t_u16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_3>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_t_u16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_4>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+ v_cmpx_u_f16 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_1>`
+ v_cmpx_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx90a_sdst_6>`, :ref:`src0<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>`, :ref:`src1<amdgpu_synid_gfx90a_src_1>`::ref:`m<amdgpu_synid_gfx90a_m_1>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f64 :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a_src_2>`, :ref:`vsrc1<amdgpu_synid_gfx90a_vsrc_2>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+ :hidden:
+
+ gfx90a_dst
+ gfx90a_fx_operand
+ gfx90a_hwreg
+ gfx90a_imask
+ gfx90a_imm16
+ gfx90a_imm16_1
+ gfx90a_imm16_2
+ gfx90a_label
+ gfx90a_m
+ gfx90a_m_1
+ gfx90a_msg
+ gfx90a_opt
+ gfx90a_probe
+ gfx90a_saddr
+ gfx90a_saddr_1
+ gfx90a_sbase
+ gfx90a_sbase_1
+ gfx90a_sbase_2
+ gfx90a_sdata
+ gfx90a_sdata_1
+ gfx90a_sdata_2
+ gfx90a_sdata_3
+ gfx90a_sdata_4
+ gfx90a_sdata_5
+ gfx90a_sdst
+ gfx90a_sdst_1
+ gfx90a_sdst_2
+ gfx90a_sdst_3
+ gfx90a_sdst_4
+ gfx90a_sdst_5
+ gfx90a_sdst_6
+ gfx90a_sdst_7
+ gfx90a_simm32
+ gfx90a_simm32_1
+ gfx90a_simm32_2
+ gfx90a_soffset
+ gfx90a_soffset_1
+ gfx90a_soffset_2
+ gfx90a_src
+ gfx90a_src_1
+ gfx90a_src_10
+ gfx90a_src_11
+ gfx90a_src_2
+ gfx90a_src_3
+ gfx90a_src_4
+ gfx90a_src_5
+ gfx90a_src_6
+ gfx90a_src_7
+ gfx90a_src_8
+ gfx90a_src_9
+ gfx90a_srsrc
+ gfx90a_srsrc_1
+ gfx90a_ssamp
+ gfx90a_ssrc
+ gfx90a_ssrc_1
+ gfx90a_ssrc_2
+ gfx90a_ssrc_3
+ gfx90a_ssrc_4
+ gfx90a_ssrc_5
+ gfx90a_ssrc_6
+ gfx90a_ssrc_7
+ gfx90a_ssrc_8
+ gfx90a_type_deviation
+ gfx90a_vaddr
+ gfx90a_vaddr_1
+ gfx90a_vaddr_2
+ gfx90a_vaddr_3
+ gfx90a_vaddr_4
+ gfx90a_vaddr_5
+ gfx90a_vcc
+ gfx90a_vdata
+ gfx90a_vdata0
+ gfx90a_vdata0_1
+ gfx90a_vdata1
+ gfx90a_vdata1_1
+ gfx90a_vdata_1
+ gfx90a_vdata_10
+ gfx90a_vdata_2
+ gfx90a_vdata_3
+ gfx90a_vdata_4
+ gfx90a_vdata_5
+ gfx90a_vdata_6
+ gfx90a_vdata_7
+ gfx90a_vdata_8
+ gfx90a_vdata_9
+ gfx90a_vdst
+ gfx90a_vdst_1
+ gfx90a_vdst_10
+ gfx90a_vdst_11
+ gfx90a_vdst_12
+ gfx90a_vdst_13
+ gfx90a_vdst_14
+ gfx90a_vdst_15
+ gfx90a_vdst_16
+ gfx90a_vdst_17
+ gfx90a_vdst_18
+ gfx90a_vdst_19
+ gfx90a_vdst_2
+ gfx90a_vdst_3
+ gfx90a_vdst_4
+ gfx90a_vdst_5
+ gfx90a_vdst_6
+ gfx90a_vdst_7
+ gfx90a_vdst_8
+ gfx90a_vdst_9
+ gfx90a_vsrc
+ gfx90a_vsrc_1
+ gfx90a_vsrc_2
+ gfx90a_vsrc_3
+ gfx90a_vsrc_4
+ gfx90a_vsrc_5
+ gfx90a_waitcnt
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
index b382317fa5a9b..b7acd418e89d4 100644
--- a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
@@ -10,10 +10,8 @@
soffset
===========================
-An unsigned byte offset added to the base address to get memory address.
-
-.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
+An unsigned 20-bit offset added to the base address to get memory address.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
index 09ef0227ae11b..30763e7f9bbbe 100644
--- a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
@@ -15,8 +15,6 @@ An offset added to the base address to get memory address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
-.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
-
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx90a_dst.rst b/llvm/docs/AMDGPU/gfx90a_dst.rst
new file mode 100644
index 0000000000000..7beda28c51d91
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_dst.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_dst:
+
+dst
+===
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx90a_fx_operand.rst b/llvm/docs/AMDGPU/gfx90a_fx_operand.rst
new file mode 100644
index 0000000000000..e58f7c3cd6e41
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_fx_operand.rst
@@ -0,0 +1,16 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_fx_operand:
+
+FX Operand
+==========
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
diff --git a/llvm/docs/AMDGPU/gfx90a_hwreg.rst b/llvm/docs/AMDGPU/gfx90a_hwreg.rst
new file mode 100644
index 0000000000000..6e100b59f08db
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_hwreg.rst
@@ -0,0 +1,73 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_hwreg:
+
+hwreg
+=====
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+ ======= ===================== ============
+ Bits Description Value Range
+ ======= ===================== ============
+ 5:0 Register *id*. 0..63
+ 10:6 First bit *offset*. 0..31
+ 15:11 *Size* in bits. 1..32
+ ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+ ==================================== ============================================================================
+ Hwreg Value Syntax Description
+ ==================================== ============================================================================
+ hwreg({0..63}) All bits of a register indicated by its *id*.
+ hwreg(<*name*>) All bits of a register indicated by its *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
+ ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+ =================== ==========================================
+ Name Description
+ =================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID Id of wave, simd, compute unit, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+ reg = 1
+ offset = 2
+ size = 4
+ hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+ s_getreg_b32 s2, 0x1881
+ s_getreg_b32 s2, hwreg_enc // the same as above
+ s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
+ s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
+
+ s_getreg_b32 s2, hwreg(15)
+ s_getreg_b32 s2, hwreg(51, 1, 31)
+ s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
diff --git a/llvm/docs/AMDGPU/gfx90a_imask.rst b/llvm/docs/AMDGPU/gfx90a_imask.rst
new file mode 100644
index 0000000000000..a6a45488cbc70
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_imask.rst
@@ -0,0 +1,65 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_imask:
+
+imask
+=====
+
+This operand is a mask which controls indexing mode for operands of subsequent instructions.
+Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
+Value 1 enables indexing and value 0 disables it.
+
+ ===== ========================================
+ Bit Meaning
+ ===== ========================================
+ 0 Enables or disables *src0* indexing.
+ 1 Enables or disables *src1* indexing.
+ 2 Enables or disables *src2* indexing.
+ 3 Enables or disables *dst* indexing.
+ ===== ========================================
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
+* A *gpr_idx* value described below.
+
+ ==================================== ===========================================
+ Gpr_idx Value Syntax Description
+ ==================================== ===========================================
+ gpr_idx(*<operands>*) Enable indexing for specified *operands*
+ and disable it for the rest.
+ *Operands* is a comma-separated list of
+ values which may include:
+
+ * "SRC0" - enable *src0* indexing.
+
+ * "SRC1" - enable *src1* indexing.
+
+ * "SRC2" - enable *src2* indexing.
+
+ * "DST" - enable *dst* indexing.
+
+ Each of these values may be specified only
+ once.
+
+ *Operands* list may be empty; this syntax
+ disables indexing for all operands.
+ ==================================== ===========================================
+
+Examples:
+
+.. parsed-literal::
+
+ s_set_gpr_idx_mode 0
+ s_set_gpr_idx_mode gpr_idx() // the same as above
+
+ s_set_gpr_idx_mode 15
+ s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
+ s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
+
+ s_set_gpr_idx_mode gpr_idx(DST,SRC1)
diff --git a/llvm/docs/AMDGPU/gfx90a_imm16.rst b/llvm/docs/AMDGPU/gfx90a_imm16.rst
new file mode 100644
index 0000000000000..8d43cf4af0676
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_imm16.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_imm16:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx90a_imm16_1.rst b/llvm/docs/AMDGPU/gfx90a_imm16_1.rst
new file mode 100644
index 0000000000000..f270aa4338593
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_imm16_1.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_imm16_1:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
diff --git a/llvm/docs/AMDGPU/gfx90a_imm16_2.rst b/llvm/docs/AMDGPU/gfx90a_imm16_2.rst
new file mode 100644
index 0000000000000..17fce930d9c6d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_imm16_2.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_imm16_2:
+
+imm16
+=====
+
+A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx90a_label.rst b/llvm/docs/AMDGPU/gfx90a_label.rst
new file mode 100644
index 0000000000000..613f6d3da5cf4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_label.rst
@@ -0,0 +1,36 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_label:
+
+label
+=====
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+ offset = 30
+ label_1:
+ label_2 = . + 4
+
+ s_branch 32
+ s_branch offset + 2
+ s_branch label_1
+ s_branch label_2
+ s_branch label_3
+ s_branch label_4
+
+ label_3 = label_2 + 4
+ label_4:
diff --git a/llvm/docs/AMDGPU/gfx90a_m.rst b/llvm/docs/AMDGPU/gfx90a_m.rst
new file mode 100644
index 0000000000000..501379d015352
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_m.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_m:
+
+m
+=
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx90a_m_1.rst b/llvm/docs/AMDGPU/gfx90a_m_1.rst
new file mode 100644
index 0000000000000..0d1dd6fefc793
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_m_1.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_m_1:
+
+m
+=
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx90a_msg.rst b/llvm/docs/AMDGPU/gfx90a_msg.rst
new file mode 100644
index 0000000000000..aa44d3b64f49e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_msg.rst
@@ -0,0 +1,96 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_msg:
+
+msg
+===
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+ ============ =============================== ===============
+ Bits Description Value Range
+ ============ =============================== ===============
+ 3:0 Message *type*. 0..15
+ 6:4 Optional *operation*. 0..7
+ 7:7 Unused. \-
+ 9:8 Optional *stream*. 0..3
+ 15:10 Unused. \-
+ ============ =============================== ===============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A *sendmsg* value described below.
+
+ ==================================== ====================================================
+ Sendmsg Value Syntax Description
+ ==================================== ====================================================
+ sendmsg(<*type*>) A message identified by its *type*.
+ sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
+ sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
+ with a stream *id*.
+ ==================================== ====================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Each message type supports specific operations:
+
+ ================= ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ================= ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_GET_DOORBELL 10 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_HOST_TRAP_ACK 3 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ================= ========== ============================== ============ ==========
+
+*Sendmsg* arguments are validated depending on how *type* value is specified:
+
+* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
+* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+
+Examples:
+
+.. parsed-literal::
+
+ // numeric message code
+ msg = 0x10
+ s_sendmsg 0x12
+ s_sendmsg msg + 2
+
+ // sendmsg with strict arguments validation
+ s_sendmsg sendmsg(MSG_INTERRUPT)
+ s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+ s_sendmsg sendmsg(MSG_GS, 2)
+ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+ s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+ s_sendmsg sendmsg(MSG_GET_DOORBELL)
+
+ // sendmsg with validation of value range only
+ msg = 2
+ op = 3
+ stream = 1
+ s_sendmsg sendmsg(msg, op, stream)
+ s_sendmsg sendmsg(2, GS_OP_CUT)
diff --git a/llvm/docs/AMDGPU/gfx90a_opt.rst b/llvm/docs/AMDGPU/gfx90a_opt.rst
new file mode 100644
index 0000000000000..dd035b8149e21
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_opt.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_opt:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx90a_probe.rst b/llvm/docs/AMDGPU/gfx90a_probe.rst
new file mode 100644
index 0000000000000..62c64c30d2ad6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_probe.rst
@@ -0,0 +1,24 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_probe:
+
+probe
+=====
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is truncated to 7 bits, but only 3 low bits are significant.
+
+ ============ ==============================
+ Bit Number Description
+ ============ ==============================
+ 0 Request *read* permission.
+ 1 Request *write* permission.
+ 2 Request *execute* permission.
+ ============ ==============================
diff --git a/llvm/docs/AMDGPU/gfx90a_saddr.rst b/llvm/docs/AMDGPU/gfx90a_saddr.rst
new file mode 100644
index 0000000000000..4e4c84784e9d8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_saddr.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_saddr:
+
+saddr
+=====
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx90a_saddr_1.rst b/llvm/docs/AMDGPU/gfx90a_saddr_1.rst
new file mode 100644
index 0000000000000..34d8ad7f66c79
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_saddr_1.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_saddr_1:
+
+saddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sbase.rst b/llvm/docs/AMDGPU/gfx90a_sbase.rst
new file mode 100644
index 0000000000000..669b8f2b8fc6d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sbase.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sbase:
+
+sbase
+=====
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sbase_1.rst b/llvm/docs/AMDGPU/gfx90a_sbase_1.rst
new file mode 100644
index 0000000000000..94f45c157b8dd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sbase_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sbase_1:
+
+sbase
+=====
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sbase_2.rst b/llvm/docs/AMDGPU/gfx90a_sbase_2.rst
new file mode 100644
index 0000000000000..75f00f38e100c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sbase_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sbase_2:
+
+sbase
+=====
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata.rst b/llvm/docs/AMDGPU/gfx90a_sdata.rst
new file mode 100644
index 0000000000000..80d59338c962f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata_1.rst b/llvm/docs/AMDGPU/gfx90a_sdata_1.rst
new file mode 100644
index 0000000000000..34df71ebfdaa2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata_1.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata_1:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata_2.rst b/llvm/docs/AMDGPU/gfx90a_sdata_2.rst
new file mode 100644
index 0000000000000..b0bad7c265159
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata_2.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata_2:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata_3.rst b/llvm/docs/AMDGPU/gfx90a_sdata_3.rst
new file mode 100644
index 0000000000000..9d838f5605c22
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata_3:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata_4.rst b/llvm/docs/AMDGPU/gfx90a_sdata_4.rst
new file mode 100644
index 0000000000000..fd7f62b7c4c16
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata_4:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdata_5.rst b/llvm/docs/AMDGPU/gfx90a_sdata_5.rst
new file mode 100644
index 0000000000000..7554d386093f0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdata_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdata_5:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst.rst b/llvm/docs/AMDGPU/gfx90a_sdst.rst
new file mode 100644
index 0000000000000..c1980515a1a09
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_1.rst b/llvm/docs/AMDGPU/gfx90a_sdst_1.rst
new file mode 100644
index 0000000000000..cfaedb8befa00
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_1:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_2.rst b/llvm/docs/AMDGPU/gfx90a_sdst_2.rst
new file mode 100644
index 0000000000000..58d3d7e598ec1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_2:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_3.rst b/llvm/docs/AMDGPU/gfx90a_sdst_3.rst
new file mode 100644
index 0000000000000..180f4bb68e153
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_3:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_4.rst b/llvm/docs/AMDGPU/gfx90a_sdst_4.rst
new file mode 100644
index 0000000000000..d183c0b2f1209
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_4:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_5.rst b/llvm/docs/AMDGPU/gfx90a_sdst_5.rst
new file mode 100644
index 0000000000000..a2ae6920e71d1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_5:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_6.rst b/llvm/docs/AMDGPU/gfx90a_sdst_6.rst
new file mode 100644
index 0000000000000..8a8fddc9bee35
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_6:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx90a_sdst_7.rst b/llvm/docs/AMDGPU/gfx90a_sdst_7.rst
new file mode 100644
index 0000000000000..079d3bea33c59
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_sdst_7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_sdst_7:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_simm32.rst b/llvm/docs/AMDGPU/gfx90a_simm32.rst
new file mode 100644
index 0000000000000..cb0710fdeab54
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_simm32.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_simm32:
+
+simm32
+======
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
diff --git a/llvm/docs/AMDGPU/gfx90a_simm32_1.rst b/llvm/docs/AMDGPU/gfx90a_simm32_1.rst
new file mode 100644
index 0000000000000..dbf685350326c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_simm32_1.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_simm32_1:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx90a_simm32_2.rst b/llvm/docs/AMDGPU/gfx90a_simm32_2.rst
new file mode 100644
index 0000000000000..63b8ad3d11014
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_simm32_2.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_simm32_2:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx90a_soffset.rst b/llvm/docs/AMDGPU/gfx90a_soffset.rst
new file mode 100644
index 0000000000000..1a4623404c222
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_soffset.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_soffset:
+
+soffset
+=======
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_soffset_1.rst b/llvm/docs/AMDGPU/gfx90a_soffset_1.rst
new file mode 100644
index 0000000000000..13728978887e1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_soffset_1.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_soffset_1:
+
+soffset
+=======
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx90a_soffset_2.rst b/llvm/docs/AMDGPU/gfx90a_soffset_2.rst
new file mode 100644
index 0000000000000..e94fda005b2a3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_soffset_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_soffset_2:
+
+soffset
+=======
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src.rst b/llvm/docs/AMDGPU/gfx90a_src.rst
new file mode 100644
index 0000000000000..56a69b4b8313d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_1.rst b/llvm/docs/AMDGPU/gfx90a_src_1.rst
new file mode 100644
index 0000000000000..a939cecc6796d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_1:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_10.rst b/llvm/docs/AMDGPU/gfx90a_src_10.rst
new file mode 100644
index 0000000000000..d53a92673af05
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_10.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_10:
+
+src
+===
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_11.rst b/llvm/docs/AMDGPU/gfx90a_src_11.rst
new file mode 100644
index 0000000000000..bfcf55f08aa22
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_11.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_11:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_2.rst b/llvm/docs/AMDGPU/gfx90a_src_2.rst
new file mode 100644
index 0000000000000..f4750b299e133
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_2:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_3.rst b/llvm/docs/AMDGPU/gfx90a_src_3.rst
new file mode 100644
index 0000000000000..7646f4baa9d6c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_3:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_4.rst b/llvm/docs/AMDGPU/gfx90a_src_4.rst
new file mode 100644
index 0000000000000..691af89ef8a64
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_4:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_5.rst b/llvm/docs/AMDGPU/gfx90a_src_5.rst
new file mode 100644
index 0000000000000..ece72dfc7d72d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_5:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_6.rst b/llvm/docs/AMDGPU/gfx90a_src_6.rst
new file mode 100644
index 0000000000000..6c25799128160
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_6:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_7.rst b/llvm/docs/AMDGPU/gfx90a_src_7.rst
new file mode 100644
index 0000000000000..968984b379e76
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_7:
+
+src
+===
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_8.rst b/llvm/docs/AMDGPU/gfx90a_src_8.rst
new file mode 100644
index 0000000000000..dfcd66e98d0c5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_8:
+
+src
+===
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_src_9.rst b/llvm/docs/AMDGPU/gfx90a_src_9.rst
new file mode 100644
index 0000000000000..fbf03083e0da4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_src_9.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_src_9:
+
+src
+===
+
+Instruction input.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_srsrc.rst b/llvm/docs/AMDGPU/gfx90a_srsrc.rst
new file mode 100644
index 0000000000000..4330c4f5165a4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_srsrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_srsrc:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_srsrc_1.rst b/llvm/docs/AMDGPU/gfx90a_srsrc_1.rst
new file mode 100644
index 0000000000000..77a94170df2b4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_srsrc_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_srsrc_1:
+
+srsrc
+=====
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssamp.rst b/llvm/docs/AMDGPU/gfx90a_ssamp.rst
new file mode 100644
index 0000000000000..9894783933733
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssamp.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssamp:
+
+ssamp
+=====
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc.rst b/llvm/docs/AMDGPU/gfx90a_ssrc.rst
new file mode 100644
index 0000000000000..c152bb25940eb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_1.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_1.rst
new file mode 100644
index 0000000000000..809f04b8a1a39
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_1:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_2.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_2.rst
new file mode 100644
index 0000000000000..b47ed39496efb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_2:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_3.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_3.rst
new file mode 100644
index 0000000000000..759634338e9e6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_3:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_4.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_4.rst
new file mode 100644
index 0000000000000..709278b864ea3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_4:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_5.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_5.rst
new file mode 100644
index 0000000000000..cf95369da31a9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_5:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_6.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_6.rst
new file mode 100644
index 0000000000000..bacb7be2aed36
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_6:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_7.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_7.rst
new file mode 100644
index 0000000000000..c4c5c60554b79
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_7:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx90a_ssrc_8.rst b/llvm/docs/AMDGPU/gfx90a_ssrc_8.rst
new file mode 100644
index 0000000000000..cd435b19a71c2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_ssrc_8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_ssrc_8:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx90a_type_deviation.rst b/llvm/docs/AMDGPU/gfx90a_type_deviation.rst
new file mode 100644
index 0000000000000..8da1cd77cb3fb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_type_deviation.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_type_deviation:
+
+Type Deviation
+==============
+
+*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr.rst b/llvm/docs/AMDGPU/gfx90a_vaddr.rst
new file mode 100644
index 0000000000000..511d90fa8d8e2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr:
+
+vaddr
+=====
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr_1.rst b/llvm/docs/AMDGPU/gfx90a_vaddr_1.rst
new file mode 100644
index 0000000000000..163642c0c1361
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr_1:
+
+vaddr
+=====
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr_2.rst b/llvm/docs/AMDGPU/gfx90a_vaddr_2.rst
new file mode 100644
index 0000000000000..ce380368eb817
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr_2.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr_2:
+
+vaddr
+=====
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx90a_saddr>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid_gfx90a_saddr>` + :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx90a_saddr>` is not :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr_3.rst b/llvm/docs/AMDGPU/gfx90a_vaddr_3.rst
new file mode 100644
index 0000000000000..3ad704705b488
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr_3.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr_3:
+
+vaddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr_4.rst b/llvm/docs/AMDGPU/gfx90a_vaddr_4.rst
new file mode 100644
index 0000000000000..5647d4ab33f6a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr_4.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr_4:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
+
+ Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+ Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vaddr_5.rst b/llvm/docs/AMDGPU/gfx90a_vaddr_5.rst
new file mode 100644
index 0000000000000..19209225c789e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vaddr_5.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vaddr_5:
+
+vaddr
+=====
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vcc.rst b/llvm/docs/AMDGPU/gfx90a_vcc.rst
new file mode 100644
index 0000000000000..243764ed6ed0b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vcc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vcc:
+
+vcc
+===
+
+Vector condition code.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata.rst b/llvm/docs/AMDGPU/gfx90a_vdata.rst
new file mode 100644
index 0000000000000..8f3d77feb62a3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata0.rst b/llvm/docs/AMDGPU/gfx90a_vdata0.rst
new file mode 100644
index 0000000000000..f93566d11f496
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata0:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata0_1.rst b/llvm/docs/AMDGPU/gfx90a_vdata0_1.rst
new file mode 100644
index 0000000000000..bb40b08ab5ef9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata0_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata0_1:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata1.rst b/llvm/docs/AMDGPU/gfx90a_vdata1.rst
new file mode 100644
index 0000000000000..d30c31aff9321
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata1:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata1_1.rst b/llvm/docs/AMDGPU/gfx90a_vdata1_1.rst
new file mode 100644
index 0000000000000..6c39bb7817968
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata1_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata1_1:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_1.rst b/llvm/docs/AMDGPU/gfx90a_vdata_1.rst
new file mode 100644
index 0000000000000..9dbeaed23814b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_1:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_10.rst b/llvm/docs/AMDGPU/gfx90a_vdata_10.rst
new file mode 100644
index 0000000000000..0fa492ed28761
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_10.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_10:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_2.rst b/llvm/docs/AMDGPU/gfx90a_vdata_2.rst
new file mode 100644
index 0000000000000..11452b2e3994c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_2:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_3.rst b/llvm/docs/AMDGPU/gfx90a_vdata_3.rst
new file mode 100644
index 0000000000000..46ba3338d8c19
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_3:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_4.rst b/llvm/docs/AMDGPU/gfx90a_vdata_4.rst
new file mode 100644
index 0000000000000..1a8450038bea5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_4.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_4:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_5.rst b/llvm/docs/AMDGPU/gfx90a_vdata_5.rst
new file mode 100644
index 0000000000000..6abc50efe97c8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_5.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_5:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_6.rst b/llvm/docs/AMDGPU/gfx90a_vdata_6.rst
new file mode 100644
index 0000000000000..8deeb8de8db42
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_6.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_6:
+
+vdata
+=====
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_7.rst b/llvm/docs/AMDGPU/gfx90a_vdata_7.rst
new file mode 100644
index 0000000000000..58860a450dae3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_7:
+
+vdata
+=====
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_8.rst b/llvm/docs/AMDGPU/gfx90a_vdata_8.rst
new file mode 100644
index 0000000000000..0753155bb0e74
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_8.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_8:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdata_9.rst b/llvm/docs/AMDGPU/gfx90a_vdata_9.rst
new file mode 100644
index 0000000000000..158f7a5de4eca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdata_9.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdata_9:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst.rst b/llvm/docs/AMDGPU/gfx90a_vdst.rst
new file mode 100644
index 0000000000000..635809c2eb1ba
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_1.rst b/llvm/docs/AMDGPU/gfx90a_vdst_1.rst
new file mode 100644
index 0000000000000..955027743800b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_1:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_10.rst b/llvm/docs/AMDGPU/gfx90a_vdst_10.rst
new file mode 100644
index 0000000000000..b824f2087c8e1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_10.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_10:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_11.rst b/llvm/docs/AMDGPU/gfx90a_vdst_11.rst
new file mode 100644
index 0000000000000..36477152c56c6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_11.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_11:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_12.rst b/llvm/docs/AMDGPU/gfx90a_vdst_12.rst
new file mode 100644
index 0000000000000..01d2df9b09371
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_12.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_12:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_13.rst b/llvm/docs/AMDGPU/gfx90a_vdst_13.rst
new file mode 100644
index 0000000000000..60ea58ec1f6e7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_13.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_13:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_14.rst b/llvm/docs/AMDGPU/gfx90a_vdst_14.rst
new file mode 100644
index 0000000000000..d63a6ce179a45
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_14.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_14:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_15.rst b/llvm/docs/AMDGPU/gfx90a_vdst_15.rst
new file mode 100644
index 0000000000000..75f97e627f923
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_15.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_15:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_16.rst b/llvm/docs/AMDGPU/gfx90a_vdst_16.rst
new file mode 100644
index 0000000000000..b2028a9ed2fb1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_16.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_16:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_17.rst b/llvm/docs/AMDGPU/gfx90a_vdst_17.rst
new file mode 100644
index 0000000000000..df6d067592fb2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_17.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_17:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_18.rst b/llvm/docs/AMDGPU/gfx90a_vdst_18.rst
new file mode 100644
index 0000000000000..d9aecae4b93ab
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_18.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_18:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_19.rst b/llvm/docs/AMDGPU/gfx90a_vdst_19.rst
new file mode 100644
index 0000000000000..426b2c25fa1cd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_19.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_19:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_2.rst b/llvm/docs/AMDGPU/gfx90a_vdst_2.rst
new file mode 100644
index 0000000000000..876a2350fcf3d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_2:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_3.rst b/llvm/docs/AMDGPU/gfx90a_vdst_3.rst
new file mode 100644
index 0000000000000..53869b1a9eb06
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_3:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_4.rst b/llvm/docs/AMDGPU/gfx90a_vdst_4.rst
new file mode 100644
index 0000000000000..dbab63177b949
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_4.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_4:
+
+vdst
+====
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_5.rst b/llvm/docs/AMDGPU/gfx90a_vdst_5.rst
new file mode 100644
index 0000000000000..fba2e0a258983
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_5.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_5:
+
+vdst
+====
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_6.rst b/llvm/docs/AMDGPU/gfx90a_vdst_6.rst
new file mode 100644
index 0000000000000..f3bc6ae375830
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_6.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_6:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_7.rst b/llvm/docs/AMDGPU/gfx90a_vdst_7.rst
new file mode 100644
index 0000000000000..c4a50804eac8b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_7.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_7:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_8.rst b/llvm/docs/AMDGPU/gfx90a_vdst_8.rst
new file mode 100644
index 0000000000000..01b73aee14622
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_8:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vdst_9.rst b/llvm/docs/AMDGPU/gfx90a_vdst_9.rst
new file mode 100644
index 0000000000000..9d2a42dcff3bf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vdst_9.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vdst_9:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc.rst b/llvm/docs/AMDGPU/gfx90a_vsrc.rst
new file mode 100644
index 0000000000000..5b5934e19d28f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc_1.rst b/llvm/docs/AMDGPU/gfx90a_vsrc_1.rst
new file mode 100644
index 0000000000000..b9e7b0ed98fc4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc_1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc_1:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc_2.rst b/llvm/docs/AMDGPU/gfx90a_vsrc_2.rst
new file mode 100644
index 0000000000000..1793c49e8b501
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc_2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc_2:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc_3.rst b/llvm/docs/AMDGPU/gfx90a_vsrc_3.rst
new file mode 100644
index 0000000000000..13bffbad38e20
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc_3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc_3:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc_4.rst b/llvm/docs/AMDGPU/gfx90a_vsrc_4.rst
new file mode 100644
index 0000000000000..29f30b421869b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc_4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc_4:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_vsrc_5.rst b/llvm/docs/AMDGPU/gfx90a_vsrc_5.rst
new file mode 100644
index 0000000000000..fbfb8795691e1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_vsrc_5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_vsrc_5:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx90a_waitcnt.rst b/llvm/docs/AMDGPU/gfx90a_waitcnt.rst
new file mode 100644
index 0000000000000..8f503df9b08b2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx90a_waitcnt.rst
@@ -0,0 +1,64 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx90a_waitcnt:
+
+waitcnt
+=======
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+ ========== ========= ================================================ ============
+ High Bits Low Bits Description Value Range
+ ========== ========= ================================================ ============
+ 15:14 3:0 VM_CNT: vector memory operations count. 0..63
+ \- 6:4 EXP_CNT: export count. 0..7
+ \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
+ ========== ========= ================================================ ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
+
+ ====================== ======================================================================
+ Syntax Description
+ ====================== ======================================================================
+ vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
+ expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+ lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+ vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
+ expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+ lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+ ====================== ======================================================================
+
+These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ vm_cnt = 1
+ exp_cnt = 2
+ lgkm_cnt = 3
+ cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
+
+ s_waitcnt cnt
+ s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
+ s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
+ s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
+
+ s_waitcnt vmcnt(1)
+ s_waitcnt expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+ s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
diff --git a/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
index fdc4b09ee8163..7c23cae0eb017 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
@@ -10,10 +10,8 @@
soffset
===========================
-An unsigned byte offset added to the base address to get memory address.
-
-.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
+An unsigned 20-bit offset added to the base address to get memory address.
*Size:* 1 dword.
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
index a58df5593730e..a7f6867d863db 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
+++ b/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
@@ -15,8 +15,6 @@ An offset added to the base address to get memory address.
* If offset is specified as a register, it supplies an unsigned byte offset.
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
-.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
-
*Size:* 1 dword.
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst
index d6a387908ef05..6f8e37f2e7d69 100644
--- a/llvm/docs/AMDGPUModifierSyntax.rst
+++ b/llvm/docs/AMDGPUModifierSyntax.rst
@@ -1032,8 +1032,8 @@ GFX10 only.
Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
-DPP/DPP16 Modifiers
--------------------
+DPP Modifiers
+-------------
GFX8, GFX9 and GFX10 only.
@@ -1115,6 +1115,77 @@ Examples:
quad_perm:[0, 1, 2, 3]
row_shl:3
+.. _amdgpu_synid_dpp32_ctrl:
+
+dpp32_ctrl
+~~~~~~~~~~
+
+Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.
+
+May be used only with GFX90A 32-bit instructions.
+
+Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
+
+ ======================================== ==================================================
+ Syntax Description
+ ======================================== ==================================================
+ quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
+ row_mirror Mirror threads within row.
+ row_half_mirror Mirror threads within 1/2 row (8 threads).
+ row_bcast:15 Broadcast 15th thread of each row to next row.
+ row_bcast:31 Broadcast thread 31 to rows 2 and 3.
+ wave_shl:1 Wavefront left shift by 1 thread.
+ wave_rol:1 Wavefront left rotate by 1 thread.
+ wave_shr:1 Wavefront right shift by 1 thread.
+ wave_ror:1 Wavefront right rotate by 1 thread.
+ row_shl:{1..15} Row shift left by 1-15 threads.
+ row_shr:{1..15} Row shift right by 1-15 threads.
+ row_ror:{1..15} Row rotate right by 1-15 threads.
+ row_newbcast:{1..15} Broadcast a thread within a row to the whole row.
+ ======================================== ==================================================
+
+Note: numeric values may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ quad_perm:[0, 1, 2, 3]
+ row_shl:3
+
+
+.. _amdgpu_synid_dpp64_ctrl:
+
+dpp64_ctrl
+~~~~~~~~~~
+
+Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.
+
+May be used only with GFX90A 64-bit instructions.
+
+Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
+
+ ======================================== ==================================================
+ Syntax Description
+ ======================================== ==================================================
+ row_newbcast:{1..15} Broadcast a thread within a row to the whole row.
+ ======================================== ==================================================
+
+Note: numeric values may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ row_newbcast:3
+
+
.. _amdgpu_synid_row_mask:
row_mask
@@ -1778,15 +1849,19 @@ See a description :ref:`here<amdgpu_synid_clamp>`.
VOP3P MFMA Modifiers
--------------------
+These modifiers may only be used with GFX908 and GFX90A.
+
.. _amdgpu_synid_cbsz:
cbsz
~~~~
+Specifies a broadcast mode.
+
=============================== ==================================================================
Syntax Description
=============================== ==================================================================
- cbsz:[{0..7}] TBD
+ cbsz:[{0..7}] A broadcast mode.
=============================== ==================================================================
Note: numeric value may be specified as either
@@ -1798,10 +1873,12 @@ an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
abid
~~~~
+Specifies matrix A group select.
+
=============================== ==================================================================
Syntax Description
=============================== ==================================================================
- abid:[{0..15}] TBD
+ abid:[{0..15}] Matrix A group select id.
=============================== ==================================================================
Note: numeric value may be specified as either
@@ -1813,10 +1890,12 @@ an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
blgp
~~~~
+Specifies matrix B lane group pattern.
+
=============================== ==================================================================
Syntax Description
=============================== ==================================================================
- blgp:[{0..7}] TBD
+ blgp:[{0..7}] Matrix B lane group pattern.
=============================== ==================================================================
Note: numeric value may be specified as either
diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index a333924feb884..d41f429bccb33 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -31,7 +31,7 @@ Vector registers. There are 256 32-bit vector registers.
A sequence of *vector* registers may be used to operate with more than 32 bits of data.
-Assembler currently supports sequences of 1, 2, 3, 4, 8 and 16 *vector* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 *vector* registers.
=================================================== ====================================================================
Syntax Description
@@ -61,7 +61,10 @@ Note: *N* and *K* must satisfy the following conditions:
* *N* <= *K*.
* 0 <= *N* <= 255.
* 0 <= *K* <= 255.
-* *K-N+1* must be equal to 1, 2, 3, 4, 8 or 16.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 8, 16 or 32.
+
+GFX90A has an additional alignment requirement: pairs of *vector* registers must be even-aligned
+(first register must be even).
Examples:
@@ -111,7 +114,7 @@ Accumulator registers. There are 256 32-bit accumulator registers.
A sequence of *accumulator* registers may be used to operate with more than 32 bits of data.
-Assembler currently supports sequences of 1, 2, 4 and 16 *accumulator* registers.
+Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 8, 16 and 32 *accumulator* registers.
=================================================== ========================================================= ====================================================================
Syntax An Alternative Syntax (SP3) Description
@@ -141,7 +144,10 @@ Note: *N* and *K* must satisfy the following conditions:
* *N* <= *K*.
* 0 <= *N* <= 255.
* 0 <= *K* <= 255.
-* *K-N+1* must be equal to 1, 2, 4 or 16.
+* *K-N+1* must be equal to 1, 2, 3, 4, 5, 6, 8, 16 or 32.
+
+GFX90A has an additional alignment requirement: pairs of *accumulator* registers must be even-aligned
+(first register must be even).
Examples:
@@ -179,9 +185,9 @@ Scalar 32-bit registers. The number of available *scalar* registers depends on G
======= ============================
A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
-Assembler currently supports sequences of 1, 2, 4, 8 and 16 *scalar* registers.
+Assembler currently supports sequences of 1, 2, 4, 8, 16 and 32 *scalar* registers.
-Pairs of *scalar* registers must be even-aligned (the first register must be even).
+Pairs of *scalar* registers must be even-aligned (first register must be even).
Sequences of 4 and more *scalar* registers must be quad-aligned.
======================================================== ====================================================================
@@ -215,7 +221,7 @@ Note: *N* and *K* must satisfy the following conditions:
* *N* <= *K*.
* 0 <= *N* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
* 0 <= *K* < *SMAX*\ , where *SMAX* is the number of available *scalar* registers.
-* *K-N+1* must be equal to 1, 2, 4, 8 or 16.
+* *K-N+1* must be equal to 1, 2, 4, 8, 16 or 32.
Examples:
@@ -269,7 +275,7 @@ The number of available *ttmp* registers depends on GPU:
A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
Assembler currently supports sequences of 1, 2, 4, 8 and 16 *ttmp* registers.
-Pairs of *ttmp* registers must be even-aligned (the first register must be even).
+Pairs of *ttmp* registers must be even-aligned (first register must be even).
Sequences of 4 and more *ttmp* registers must be quad-aligned.
============================================================= ====================================================================
@@ -413,9 +419,10 @@ registers in GFX10, but *flat_scratch* is readable/writable with the help of
*s_get_reg* and *s_set_reg* instructions.
.. _amdgpu_synid_xnack:
+.. _amdgpu_synid_xnack_mask:
-xnack
------
+xnack_mask
+----------
Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
received an *XNACK* due to a vector memory operation.
@@ -711,18 +718,6 @@ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
The value must be in the range 0..0xFFFFF.
-.. _amdgpu_synid_uimm21:
-
-uimm21
-------
-
-A 21-bit :ref:`integer number<amdgpu_synid_integer_number>`
-or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
-
-The value must be in the range 0..0x1FFFFF.
-
-.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
-
.. _amdgpu_synid_simm21:
simm21
@@ -733,8 +728,6 @@ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
The value must be in the range -0x100000..0x0FFFFF.
-.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
-
.. _amdgpu_synid_off:
off
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 4e7efd769705e..64766ff804935 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -15,6 +15,7 @@ User Guide for AMDGPU Backend
AMDGPU/AMDGPUAsmGFX904
AMDGPU/AMDGPUAsmGFX906
AMDGPU/AMDGPUAsmGFX908
+ AMDGPU/AMDGPUAsmGFX90a
AMDGPU/AMDGPUAsmGFX10
AMDGPU/AMDGPUAsmGFX1011
AMDGPUModifierSyntax
@@ -11370,6 +11371,8 @@ in this description.
:doc:`gfx909<AMDGPU/AMDGPUAsmGFX900>`
+ :doc:`gfx90a<AMDGPU/AMDGPUAsmGFX90a>`
+
:doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
:doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>`
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