[llvm] 1079870 - [llvm-mc][AArch64] HINT instruction disassembled as BTI

[Alexandros Lamprineas via llvm-commits]

Author: Alexandros Lamprineas
Date: 2021-05-14T10:05:37+01:00
New Revision: 10798709713a9b5d4ff8d8f5961b3c2fdb81d887

URL: https://github.com/llvm/llvm-project/commit/10798709713a9b5d4ff8d8f5961b3c2fdb81d887
DIFF: https://github.com/llvm/llvm-project/commit/10798709713a9b5d4ff8d8f5961b3c2fdb81d887.diff

LOG: [llvm-mc][AArch64] HINT instruction disassembled as BTI

The Arm Architecture Reference Manual says that the SystemHintOp_BTI
opcode is prefered when CRm:op2 matches 0100:xx0, but llvm-mc
currently accepts 0100:xxx, which isn't right.

Differential Revision: https://reviews.llvm.org/D102415

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrFormats.td
    llvm/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index f6d2608370028..66d3963000ad0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1483,7 +1483,7 @@ def btihint_op : Operand<i32> {
     // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
     if (!MCOp.isImm())
       return false;
-    return AArch64BTIHint::lookupBTIByEncoding((MCOp.getImm() ^ 32) >> 1) != nullptr;
+    return AArch64BTIHint::lookupBTIByEncoding(MCOp.getImm() ^ 32) != nullptr;
   }];
 }
 

diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 01ac52bd875a8..1909e79fa3a96 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -387,18 +387,18 @@ def : PSB<"csync", 0x11>;
 // BTI instruction options.
 //===----------------------------------------------------------------------===//
 
-class BTI<string name, bits<2> encoding> : SearchableTable {
+class BTI<string name, bits<3> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;
-  bits<2> Encoding;
+  bits<3> Encoding;
   let Encoding = encoding;
 }
 
-def : BTI<"c",  0b01>;
-def : BTI<"j",  0b10>;
-def : BTI<"jc", 0b11>;
+def : BTI<"c",  0b010>;
+def : BTI<"j",  0b100>;
+def : BTI<"jc", 0b110>;
 
 //===----------------------------------------------------------------------===//
 // TLBI (translation lookaside buffer invalidate) instruction options.

diff  --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 52670c6dce74a..396bae6afebdc 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2046,7 +2046,7 @@ class AArch64Operand : public MCParsedAsmOperand {
                                                        SMLoc S,
                                                        MCContext &Ctx) {
     auto Op = std::make_unique<AArch64Operand>(k_BTIHint, Ctx);
-    Op->BTIHint.Val = Val << 1 | 32;
+    Op->BTIHint.Val = Val | 32;
     Op->BTIHint.Data = Str.data();
     Op->BTIHint.Length = Str.size();
     Op->StartLoc = S;

diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 8204156d98a9e..ae42cb0f953d9 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -1152,7 +1152,7 @@ void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  unsigned btihintop = (MI->getOperand(OpNum).getImm() ^ 32) >> 1;
+  unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
   auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
   if (BTI)
     O << BTI->Name;

diff  --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt
index e15dcf5e3b777..a19f14ba422c0 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt
@@ -7,12 +7,27 @@
 [0x9f 0x24 0x03 0xd5]
 [0xdf 0x24 0x03 0xd5]
 
+[0x3f 0x24 0x03 0xd5]
+[0x7f 0x24 0x03 0xd5]
+[0xbf 0x24 0x03 0xd5]
+[0xff 0x24 0x03 0xd5]
+
 # CHECK: bti
 # CHECK: bti c
 # CHECK: bti j
 # CHECK: bti jc
 
+# CHECK: hint #33
+# CHECK: hint #35
+# CHECK: hint #37
+# CHECK: hint #39
+
 # NOBTI: hint #32
 # NOBTI: hint #34
 # NOBTI: hint #36
 # NOBTI: hint #38
+
+# NOBTI: hint #33
+# NOBTI: hint #35
+# NOBTI: hint #37
+# NOBTI: hint #39