[PATCH] D102455: [MC][ARM] Reject Thumb "ror rX, #0"

[Ryan Prichard via Phabricator via llvm-commits]

rprichard created this revision.
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The ROR instruction can only handle immediates between 1 and 31. The
would-be encoding for ROR #0 is actually the RRX instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102455

Files:
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/MC/ARM/thumb2-diagnostics.s


Index: llvm/test/MC/ARM/thumb2-diagnostics.s
===================================================================
--- llvm/test/MC/ARM/thumb2-diagnostics.s
+++ llvm/test/MC/ARM/thumb2-diagnostics.s
@@ -49,6 +49,12 @@
 @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
 @ CHECK-ERRORS-V8: invalid instruction
 
+        @ Out of range immediate for ROR.
+        @ (Assembling this instruction to "mov r1, r1" might also be OK.)
+        ror r1, r1, #0
+@ CHECK-ERRORS: invalid instruction
+@ CHECK-ERRORS: operand must be an immediate in the range [1,31]
+
         isb  #-1
         isb  #16
 @ CHECK-ERRORS: error: immediate value out of range
Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -2683,7 +2683,7 @@
 defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
 defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr,  srl>;
 defm t2ASR  : T2I_sh_ir<0b10, "asr", imm_sr,  sra>;
-defm t2ROR  : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
+defm t2ROR  : T2I_sh_ir<0b11, "ror", imm1_31, rotr>;
 
 // LSL #0 is actually MOV, and has slightly different permitted registers to
 // LSL with non-zero shift


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