[Diffusion] rGaef5bdbea197: [X86][BtVer2] Add support for all vector instructions that should match the…

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In rGaef5bdbea197d7a76d8e3aa49d61a63c502983cc#996283 <https://reviews.llvm.org/rGaef5bdbea197d7a76d8e3aa49d61a63c502983cc#996283>, @lebedev.ri wrote:

> In rGaef5bdbea197d7a76d8e3aa49d61a63c502983cc#996198 <https://reviews.llvm.org/rGaef5bdbea197d7a76d8e3aa49d61a63c502983cc#996198>, @RKSimon wrote:
>
>> My brain has rebooted many time since then, but we probably compared the PMCs numbers for dispatched fpu pipe ops, retired fpu ops and total retired ops - you should be able to find the equivalents in the 19h BKDG, hopefully they are published like they were for Jaguar.
>
> Oh well. There are no per-pipe dispatch counters! :/
> There are counters for ops dispatched out of decoder to Int/FP units,
> but that clearly includes these zero-cycle instructions.
> (It also includes renameable `mov`es.)
>
> Perhaps MCA overestimates the throughput (due to not modelling decoder/???).

I've tried everything i can think of, and i'm going to just assume that `AMD SOG 19h` is wrong,
and `xorps %xmm0, %xmm0` is not zero-cycle.
Thanks.


BRANCHES
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https://reviews.llvm.org/rGaef5bdbea197