[PATCH] D102396: [RISCV][test] Add new tests for or/xor

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

The new test will should how

  ; RV32IBS-NEXT:    lui a1, 1
  ; RV32IBS-NEXT:    addi a1, a1, 2
  ; RV32IBS-NEXT:    xor a0, a0, a1

are optimized to

  binvi a0, 12
  binvi a0, 2


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102396/new/

https://reviews.llvm.org/D102396