[PATCH] D102393: [DAGCombiner] Relax an assertion to an early return

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: spatel, craig.topper, RKSimon, lebedev.ri.
Herald added subscribers: ecnelises, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

The select-of-constants transform was asserting that its constant vector
inputs did not implicitly truncate their input without that as an
explicit precondition to the function. This patch relaxes that assertion
into an early return to skip the optimization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102393

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/rvv/select-sra.ll


Index: llvm/test/CodeGen/RISCV/rvv/select-sra.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/select-sra.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
+
+; This test checks a regression in the select-to-sra transform, which was
+; asserting (without a precondition) when the vector constants implicitly
+; truncated their inputs, as we do on RV64.
+define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
+; RV32-LABEL: vselect_of_consts:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a0, 284280
+; RV32-NEXT:    addi a0, a0, 291
+; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
+; RV32-NEXT:    vmv.v.x v25, a0
+; RV32-NEXT:    lui a0, 214376
+; RV32-NEXT:    addi a0, a0, -2030
+; RV32-NEXT:    vmerge.vxm v8, v25, a0, v0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vselect_of_consts:
+; RV64:       # %bb.0:
+; RV64-NEXT:    lui a0, 284280
+; RV64-NEXT:    addiw a0, a0, 291
+; RV64-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
+; RV64-NEXT:    vmv.v.x v25, a0
+; RV64-NEXT:    lui a0, 214376
+; RV64-NEXT:    addiw a0, a0, -2030
+; RV64-NEXT:    vmerge.vxm v8, v25, a0, v0
+; RV64-NEXT:    ret
+  %v = select <4 x i1> %cc, <4 x i32> <i32 878082066, i32 878082066, i32 878082066, i32 878082066>, <4 x i32> <i32 1164411171, i32 1164411171, i32 1164411171, i32 1164411171>
+  ret <4 x i32> %v
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9225,8 +9225,8 @@
   SDValue Cond = N->getOperand(0);
   SDValue C1 = N->getOperand(1);
   SDValue C2 = N->getOperand(2);
-  assert(isConstantOrConstantVector(C1) && isConstantOrConstantVector(C2) &&
-         "Expected select-of-constants");
+  if (!isConstantOrConstantVector(C1) || !isConstantOrConstantVector(C2))
+    return SDValue();
 
   EVT VT = N->getValueType(0);
   if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() ||


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102393.345085.patch
Type: text/x-patch
Size: 2347 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210513/83212d38/attachment.bin>