[PATCH] D99434: [TSAN] Honor failure memory orders in AtomicCAS

[Bruno Cardoso Lopes via Phabricator via llvm-commits]

bruno added inline comments.


================
Comment at: compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp:437
+
+    if (success && write_lock)
       s->mtx.Unlock();
----------------
dvyukov wrote:
> "success &&" is unnecessary here right?
> I see it's not harmful, but it also makes me a but nervous because we used just the "write_lock" condition when locking, but we use a different one when unlocking. This is not symmetric and have some potential to get out of sync, so I would drop "success &&" part here.
> 
No problemo, will do. Thanks for the careful review!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99434/new/

https://reviews.llvm.org/D99434