[PATCH] D102297: [X86] Modify LOOP*, HLT control flow attributes, add TAILJMP encoding

[Amir Ayupov via Phabricator via llvm-commits]

Amir created this revision.
Amir added reviewers: craig.topper, epastor, thakis, rnk.
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Add missing control flow attributes:

- LOOP*: isBranch, isTerminator
- HLT: isTerminator

Add encoding information for TAILJMP


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102297

Files:
  llvm/lib/Target/X86/X86InstrControl.td
  llvm/lib/Target/X86/X86InstrSystem.td


Index: llvm/lib/Target/X86/X86InstrSystem.td
===================================================================
--- llvm/lib/Target/X86/X86InstrSystem.td
+++ llvm/lib/Target/X86/X86InstrSystem.td
@@ -39,7 +39,8 @@
                    "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
 }
 
-def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
+let isTerminator = 1 in
+  def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
 
 // Interrupt and SysCall Instructions.
Index: llvm/lib/Target/X86/X86InstrControl.td
===================================================================
--- llvm/lib/Target/X86/X86InstrControl.td
+++ llvm/lib/Target/X86/X86InstrControl.td
@@ -206,7 +206,7 @@
 }
 
 // Loop instructions
-let SchedRW = [WriteJump] in {
+let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
 def LOOP   : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
 def LOOPE  : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
@@ -297,14 +297,16 @@
   def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset),
                            []>, Sched<[WriteJumpLd]>;
 
-  def TAILJMPd : PseudoI<(outs), (ins i32imm_brtarget:$dst),
-                         []>, Sched<[WriteJump]>;
+  def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), (ins i32imm_brtarget:$dst),
+                           "jmp\t$dst", []>, Sched<[WriteJump]>;
 
-  def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
-                         []>, Sched<[WriteJump]>;
-  let mayLoad = 1 in
-  def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst),
-                         []>, Sched<[WriteJumpLd]>;
+  let isIndirectBranch = 1 in {
+    def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
+                     "jmp{l}\t{*}$dst", []>, Sched<[WriteJump]>;
+    let mayLoad = 1 in
+    def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
+                     "jmp{l}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
+  }
 }
 
 // Conditional tail calls are similar to the above, but they are branches


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