[PATCH] D102205: CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 344968.
arsenm retitled this revision from "CodeGen: Make all passes preserve MachineOptimizationRemarkEmitterPass" to "CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis".
arsenm edited the summary of this revision.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102205/new/

https://reviews.llvm.org/D102205

Files:
  llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
  llvm/test/CodeGen/AMDGPU/llc-pipeline.ll


Index: llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -367,7 +367,6 @@
 ; GCN-O1-NEXT:         SI lower SGPR spill instructions
 ; GCN-O1-NEXT:         Virtual Register Map
 ; GCN-O1-NEXT:         Live Register Matrix
-; GCN-O1-NEXT:         Machine Optimization Remark Emitter
 ; GCN-O1-NEXT:         Greedy Register Allocator
 ; GCN-O1-NEXT:         GCN NSA Reassign
 ; GCN-O1-NEXT:         Virtual Register Rewriter
@@ -655,7 +654,6 @@
 ; GCN-O1-OPTS-NEXT:         SI lower SGPR spill instructions
 ; GCN-O1-OPTS-NEXT:         Virtual Register Map
 ; GCN-O1-OPTS-NEXT:         Live Register Matrix
-; GCN-O1-OPTS-NEXT:         Machine Optimization Remark Emitter
 ; GCN-O1-OPTS-NEXT:         Greedy Register Allocator
 ; GCN-O1-OPTS-NEXT:         GCN NSA Reassign
 ; GCN-O1-OPTS-NEXT:         Virtual Register Rewriter
@@ -944,7 +942,6 @@
 ; GCN-O2-NEXT:         SI lower SGPR spill instructions
 ; GCN-O2-NEXT:         Virtual Register Map
 ; GCN-O2-NEXT:         Live Register Matrix
-; GCN-O2-NEXT:         Machine Optimization Remark Emitter
 ; GCN-O2-NEXT:         Greedy Register Allocator
 ; GCN-O2-NEXT:         GCN NSA Reassign
 ; GCN-O2-NEXT:         Virtual Register Rewriter
@@ -1246,7 +1243,6 @@
 ; GCN-O3-NEXT:         SI lower SGPR spill instructions
 ; GCN-O3-NEXT:         Virtual Register Map
 ; GCN-O3-NEXT:         Live Register Matrix
-; GCN-O3-NEXT:         Machine Optimization Remark Emitter
 ; GCN-O3-NEXT:         Greedy Register Allocator
 ; GCN-O3-NEXT:         GCN NSA Reassign
 ; GCN-O3-NEXT:         Virtual Register Rewriter
Index: llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
===================================================================
--- llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
+++ llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
@@ -93,7 +93,7 @@
 #define ORE_NAME "machine-opt-remark-emitter"
 
 INITIALIZE_PASS_BEGIN(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name,
-                      false, true)
+                      true, true)
 INITIALIZE_PASS_DEPENDENCY(LazyMachineBlockFrequencyInfoPass)
 INITIALIZE_PASS_END(MachineOptimizationRemarkEmitterPass, ORE_NAME, ore_name,
-                    false, true)
+                    true, true)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102205.344968.patch
Type: text/x-patch
Size: 2388 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210512/295193c5/attachment.bin>