[llvm] a383d32 - [TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2021-05-12T14:09:05+01:00
New Revision: a383d325f6c6c8d9bb52d1da221d9a144dfc475c

URL: https://github.com/llvm/llvm-project/commit/a383d325f6c6c8d9bb52d1da221d9a144dfc475c
DIFF: https://github.com/llvm/llvm-project/commit/a383d325f6c6c8d9bb52d1da221d9a144dfc475c.diff

LOG: [TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.

In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.

Differential Revision: https://reviews.llvm.org/D102318

Added: 
    

Modified: 
    llvm/lib/CodeGen/TargetRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index e95e089e63ae..f4bb71535f7f 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -267,8 +267,9 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
   }
 
   // Mask out the reserved registers
-  BitVector Reserved = getReservedRegs(MF);
-  Allocatable &= Reserved.flip();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  const BitVector &Reserved = MRI.getReservedRegs();
+  Allocatable.reset(Reserved);
 
   return Allocatable;
 }