[llvm] 6906950 - [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-05-11T12:38:53-07:00
New Revision: 69069509b2d3cb0e0bcf6e38e0ab05c432adc763

URL: https://github.com/llvm/llvm-project/commit/69069509b2d3cb0e0bcf6e38e0ab05c432adc763
DIFF: https://github.com/llvm/llvm-project/commit/69069509b2d3cb0e0bcf6e38e0ab05c432adc763.diff

LOG: [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrGISel.td
    llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 455268cab2c1..2b39cebbf93f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -132,28 +132,33 @@ def G_TRN2 : AArch64GenericInstruction {
 def G_EXT: AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
+  let hasSideEffects = 0;
 }
 
 // Represents a vector G_ASHR with an immediate.
 def G_VASHR : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
+  let hasSideEffects = 0;
 }
 
 // Represents a vector G_LSHR with an immediate.
 def G_VLSHR : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
+  let hasSideEffects = 0;
 }
 
 // Represents an integer to FP conversion on the FPR bank.
 def G_SITOF : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
+  let hasSideEffects = 0;
 }
 def G_UITOF : AArch64GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src);
+  let hasSideEffects = 0;
 }
 
 def G_FCMEQ : AArch64GenericInstruction {

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
index c97ed4d52724..38697342459b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
@@ -19,10 +19,12 @@ body:             |
     ; CHECK: %v1:fpr64 = COPY $d0
     ; CHECK: %v2:fpr64 = COPY $d1
     ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
+    ; CHECK: $d0 = COPY %shuf
     %v1:fpr(<8 x s8>) = COPY $d0
     %v2:fpr(<8 x s8>) = COPY $d1
     %3:gpr(s32) = G_CONSTANT i32 3
     %shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
+    $d0 = COPY %shuf
 
 ...
 ---
@@ -40,10 +42,12 @@ body:             |
     ; CHECK: %v1:fpr128 = COPY $q0
     ; CHECK: %v2:fpr128 = COPY $q1
     ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
+    ; CHECK: $q0 = COPY %shuf
     %v1:fpr(<16 x s8>) = COPY $q0
     %v2:fpr(<16 x s8>) = COPY $q1
     %3:gpr(s32) = G_CONSTANT i32 3
     %shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
+    $q0 = COPY %shuf
 
 ...
 ---
@@ -61,10 +65,12 @@ body:             |
     ; CHECK: %v1:fpr64 = COPY $d0
     ; CHECK: %v2:fpr64 = COPY $d1
     ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
+    ; CHECK: $d0 = COPY %shuf
     %v1:fpr(<4 x s16>) = COPY $d0
     %v2:fpr(<4 x s16>) = COPY $d1
     %3:gpr(s32) = G_CONSTANT i32 6
     %shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
+    $d0 = COPY %shuf
 
 ...
 ---
@@ -82,10 +88,12 @@ body:             |
     ; CHECK: %v1:fpr128 = COPY $q0
     ; CHECK: %v2:fpr128 = COPY $q1
     ; CHECK: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
+    ; CHECK: $q0 = COPY %shuf
     %v1:fpr(<8 x s16>) = COPY $q0
     %v2:fpr(<8 x s16>) = COPY $q1
     %3:gpr(s32) = G_CONSTANT i32 10
     %shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
+    $q0 = COPY %shuf
 ...
 
 ...
@@ -104,10 +112,12 @@ body:             |
     ; CHECK: %v1:fpr128 = COPY $q0
     ; CHECK: %v2:fpr128 = COPY $q1
     ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
+    ; CHECK: $q0 = COPY %shuf
     %v1:fpr(<4 x s32>) = COPY $q0
     %v2:fpr(<4 x s32>) = COPY $q1
     %3:gpr(s32) = G_CONSTANT i32 12
     %shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
+    $q0 = COPY %shuf
 
 ...
 ---
@@ -125,10 +135,12 @@ body:             |
     ; CHECK: %v1:fpr64 = COPY $d0
     ; CHECK: %v2:fpr64 = COPY $d1
     ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
+    ; CHECK: $d0 = COPY %shuf
     %v1:fpr(<2 x s32>) = COPY $d0
     %v2:fpr(<2 x s32>) = COPY $d1
     %3:gpr(s32) = G_CONSTANT i32 2
     %shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
+    $d0 = COPY %shuf
 
 ...
 ---
@@ -146,8 +158,10 @@ body:             |
     ; CHECK: %v1:fpr128 = COPY $q0
     ; CHECK: %v2:fpr128 = COPY $q1
     ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
+    ; CHECK: $q0 = COPY %shuf
     %v1:fpr(<2 x s64>) = COPY $q0
     %v2:fpr(<2 x s64>) = COPY $q1
     %3:gpr(s32) = G_CONSTANT i32 2
     %shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
+    $q0 = COPY %shuf
 ...