[PATCH] D102255: [SelectionDAG] Generate scoped AA metadata when loweing memcpy.

[Michael Liao via Phabricator via llvm-commits]

hliao added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/arm64-2012-05-07-MemcpyAlignBug.ll:12
 ; CHECK-NEXT: ldr  [[VAL2:x[0-9]+]], [x[[ADDR]]]
+; CHECK-NEXT: str  [[VAL2]], [x0]
 ; CHECK-NEXT: ldr  [[VAL:w[0-9]+]], [x[[ADDR]], #8]
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With that extra scoped AA info, this store is freely scheduled ahead to minimize register pressure as `cyclone` disables the latency heuristic.


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Comment at: llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll:33
+; CHECK: ldur [[REG1:q[0-9]+]], [x[[BASEREG]], #15]
+; CHECK: stur [[REG1]], [x0, #15]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i1 false)
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Similar change due to 'cyclone' schedule favors register pressure over latency.


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Comment at: llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll:36
+; CHECK-NEXT: strb w[[V2]], [x0, #2]
+; CHECK-NEXT: strb w[[V3]], [x0, #3]
 entry:
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functionality wise the same. The sequence of offset looks better in terms of the locality.


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Comment at: llvm/test/CodeGen/PowerPC/pr45301.ll:29
+; CHECK-NEXT:    stwbrx r5, 0, r3
+; CHECK-NEXT:    stwbrx r6, r3, r4
 ; CHECK-NEXT:    addi r1, r1, 112
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The same from the functionality wise but loads from that memcpy are scheduled ahead in the favor of latency hiding.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102255/new/

https://reviews.llvm.org/D102255