[PATCH] D102096: [DAGCombiner] Fix DAG combine store elimination, different address space.
Hendrik Greving via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 11 09:20:46 PDT 2021
hgreving updated this revision to Diff 344434.
hgreving added a comment.
Removed :gs versions in the test.
Added indexed store tests.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102096/new/
https://reviews.llvm.org/D102096
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/dagcombine-dead-store.ll
Index: llvm/test/CodeGen/X86/dagcombine-dead-store.ll
===================================================================
--- llvm/test/CodeGen/X86/dagcombine-dead-store.ll
+++ llvm/test/CodeGen/X86/dagcombine-dead-store.ll
@@ -5,11 +5,10 @@
; The test's 'same' and 'diff' notation depicts the pointer value exposing bugs hitting
; corner cases where the case where the pointer value is either the same, or different.
-; FIXME: DAG combine incorrectly eliminates store if pointer is of same value.
-
; CHECK-LABEL: copy_fs_same:
; CHECK: # %bb.0:
; CHECK-NEXT: movl 1, %eax
+; CHECK-NEXT: movl %eax, %fs:1
; CHECK-NEXT: retl
define i32 @copy_fs_same() {
entry:
@@ -34,6 +33,7 @@
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, 1
+; CHECK-NEXT: movl %eax, %fs:1
; CHECK-NEXT: retl
define void @output_fs_same(i32 %v) {
entry:
@@ -60,6 +60,7 @@
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %eax, 168(%ecx)
+; CHECK-NEXT: movl %eax, %fs:168(%ecx)
; CHECK-NEXT: retl
define void @output_indexed_fs_same(i32 %v, i32* %b) {
%p = getelementptr i32, i32* %b, i64 42
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17916,6 +17916,7 @@
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
ST->isUnindexed() && ST->isSimple() &&
+ Ld->getAddressSpace() == ST->getAddressSpace() &&
// There can't be any side effects between the load and store, such as
// a call or store.
Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
@@ -17929,7 +17930,8 @@
if (ST->isUnindexed() && ST->isSimple() &&
ST1->isUnindexed() && ST1->isSimple()) {
if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
- ST->getMemoryVT() == ST1->getMemoryVT()) {
+ ST->getMemoryVT() == ST1->getMemoryVT() &&
+ ST->getAddressSpace() == ST1->getAddressSpace()) {
// If this is a store followed by a store with the same value to the
// same location, then the store is dead/noop.
return Chain;
@@ -17940,7 +17942,8 @@
// BaseIndexOffset and the code below requires knowing the size
// of a vector, so bail out if MemoryVT is scalable.
!ST->getMemoryVT().isScalableVector() &&
- !ST1->getMemoryVT().isScalableVector()) {
+ !ST1->getMemoryVT().isScalableVector() &&
+ ST->getAddressSpace() == ST1->getAddressSpace()) {
const BaseIndexOffset STBase = BaseIndexOffset::match(ST, DAG);
const BaseIndexOffset ChainBase = BaseIndexOffset::match(ST1, DAG);
unsigned STBitSize = ST->getMemoryVT().getFixedSizeInBits();
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