[llvm] faebc6b - [VPlan] Register recipe for instr if the simplified value is recipe.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue May 11 06:33:10 PDT 2021
Author: Florian Hahn
Date: 2021-05-11T14:32:34+01:00
New Revision: faebc6bf108eccdfd75917636c64137f73a7bda7
URL: https://github.com/llvm/llvm-project/commit/faebc6bf108eccdfd75917636c64137f73a7bda7
DIFF: https://github.com/llvm/llvm-project/commit/faebc6bf108eccdfd75917636c64137f73a7bda7.diff
LOG: [VPlan] Register recipe for instr if the simplified value is recipe.
If the simplified VPValue is a recipe, we need to register it for Instr,
in case it needs to be recorded. The way this is handled in general may
change soon, following some post-commit comments.
This fixes PR50298.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/reduction.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index f1cf5c9f78dbb..d5dbc2e18a514 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -9067,7 +9067,12 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes(
Instr, Operands, Range, Plan)) {
// If Instr can be simplified to an existing VPValue, use it.
if (RecipeOrValue.is<VPValue *>()) {
- Plan->addVPValue(Instr, RecipeOrValue.get<VPValue *>());
+ auto *VPV = RecipeOrValue.get<VPValue *>();
+ Plan->addVPValue(Instr, VPV);
+ // If the re-used value is a recipe, register the recipe for the
+ // instruction, in case the recipe for Instr needs to be recorded.
+ if (auto *R = dyn_cast_or_null<VPRecipeBase>(VPV->getDef()))
+ RecipeBuilder.setRecipe(Instr, R);
continue;
}
// Otherwise, add the new recipe.
diff --git a/llvm/test/Transforms/LoopVectorize/reduction.ll b/llvm/test/Transforms/LoopVectorize/reduction.ll
index 66100d00c68a0..da3c9974c28d0 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction.ll
@@ -542,5 +542,66 @@ entry:
ret void
}
+; Can vectorize reduction with redundant single-operand phi input.
+define i64 @reduction_with_phi_with_one_incoming_on_backedge(i16 %n, i64* %A) {
+; CHECK-LABEL: @reduction_with_phi_with_one_incoming_on_backedge
+; CHECK: add <4 x i64>
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop.latch ]
+ %sum = phi i64 [ 0, %entry ], [ %phi.sum.next, %loop.latch ]
+ %gep.A = getelementptr i64, i64* %A, i16 %iv
+ %lv.A = load i64, i64* %gep.A
+ %sum.next = add nsw i64 %sum, %lv.A
+ br label %loop.bb
+
+loop.bb:
+ %phi.sum.next = phi i64 [ %sum.next, %loop.header ]
+ br label %loop.latch
+
+loop.latch:
+ %iv.next = add nsw i16 %iv, 1
+ %cond = icmp slt i16 %iv.next, %n
+ br i1 %cond, label %loop.header, label %exit
+
+exit:
+ %lcssa.exit = phi i64 [ %phi.sum.next, %loop.latch ]
+ ret i64 %lcssa.exit
+}
+
+; Can vectorize reduction with redundant two-operand phi input.
+define i64 @reduction_with_phi_with_two_incoming_on_backedge(i16 %n, i64* %A) {
+; CHECK-LABEL: @reduction_with_phi_with_two_incoming_on_backedge
+; CHECK: add <4 x i64>
+;
+entry:
+ br label %loop.header
+
+loop.header:
+ %iv = phi i16 [ 1, %entry ], [ %iv.next, %loop.latch ]
+ %sum = phi i64 [ 0, %entry ], [ %phi.sum.next, %loop.latch ]
+ %gep.A = getelementptr i64, i64* %A, i16 %iv
+ %lv.A = load i64, i64* %gep.A
+ %sum.next = add nsw i64 %sum, %lv.A
+ %cmp.0 = icmp eq i64 %lv.A, 29
+ br i1 %cmp.0, label %loop.bb, label %loop.latch
+
+loop.bb:
+ br label %loop.latch
+
+loop.latch:
+ %phi.sum.next = phi i64 [ %sum.next, %loop.bb ], [ %sum.next, %loop.header ]
+ %iv.next = add nsw i16 %iv, 1
+ %cond = icmp slt i16 %iv.next, %n
+ br i1 %cond, label %loop.header, label %exit
+
+exit:
+ %lcssa.exit = phi i64 [ %phi.sum.next, %loop.latch ]
+ ret i64 %lcssa.exit
+}
+
; Make sure any check-not directives are not triggered by function declarations.
; CHECK: declare
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