[PATCH] D101898: [ARM] Prevent spilling between ldrex/strex pairs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Really, using AtomicExpansionKind::LLSC at all on ARM/AArch64 is fragile; long-term, I think it still makes sense to pursue using pseudo-instructions.  But this is clearly an improvement.

I'm a little surprised that ARM::CMP_SWAP_8/ARM::CMP_SWAP_16 generating broken instructions hasn't caused any issues before.



================
Comment at: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp:2784
         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
-                              ARM::tUXTB, NextMBBI);
+                              ARM::t2UXTB, NextMBBI);
       else
----------------
I don't think we can use ARM::t2UXTB here unconditionally.  Specifically, I'm concerned about the armv8m.base target, which has ARM::t2LDREXBm/ARM::t2STREXB, but not ARM::t2UXTB.

Instead, can we add a separate ARM::tCMP_SWAP_8 instruction, with an appropriate register allocation restriction?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101898/new/

https://reviews.llvm.org/D101898