[PATCH] D101215: [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll:470
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a0, 2, e32,m1,ta,mu
+; RV32-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; RV32-NEXT:    vsoxei32.v v8, (zero), v9, v0.t
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Do you know what's going on here? This strikes me as potentially a bug?


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll:30
 ; CHECK-NEXT:    vredsum.vs v25, v25, v26
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
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These are redundant but presumably we can optimize them away (with the new VSETVLI insertion pass)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101215/new/

https://reviews.llvm.org/D101215