[llvm] f858929 - [NFCI][X86] Mark Znver3 scheduling model as complete

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2021-05-09T01:07:07+03:00
New Revision: f8589292084b41fc70da93fb1e23bb576bd1f8f3

URL: https://github.com/llvm/llvm-project/commit/f8589292084b41fc70da93fb1e23bb576bd1f8f3
DIFF: https://github.com/llvm/llvm-project/commit/f8589292084b41fc70da93fb1e23bb576bd1f8f3.diff

LOG: [NFCI][X86] Mark Znver3 scheduling model as complete

To the best of my knowledge, all instructions are modelled,
and have reasonable values to them; flipping the switch
doesn't cause any diff for MCA tests, so either we're good,
or we have test coverage gaps.

I'm not really sure why no other X86 sched model is marked as complete.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver3.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index 8f3d8de9917e..4f75150bd2a8 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -61,7 +61,7 @@ def Znver3Model : SchedMachineModel {
   // We haven't catered all instructions.
   // So, we reset the value of this variable so as to
   // say that the model is incomplete.
-  let CompleteModel = 0;
+  let CompleteModel = 1;
 }
 
 let SchedModel = Znver3Model in {
@@ -506,6 +506,9 @@ defm : Zn3WriteResInt<WriteStore, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatenc
 defm : Zn3WriteResInt<WriteStoreNT, [Zn3AGU012, Zn3Store], Znver3Model.StoreLatency, [1, 2], 1>;
 defm : Zn3WriteResInt<WriteMove, [Zn3ALU0123], 1, [4], 1>;
 
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
 def Zn3WriteMOVBE16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
   let Latency = Znver3Model.LoadLatency;
   let ResourceCycles = [1, 1, 4];