[PATCH] D101939: [AMDGPU] Disable the SIFormMemoryClauses pass at -O1

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D101939#2745028 <https://reviews.llvm.org/D101939#2745028>, @arsenm wrote:

> In D101939#2744979 <https://reviews.llvm.org/D101939#2744979>, @arsenm wrote:
>
>> It's long been on my todo list to replace reserved registers with reserved reg units which should provide a similar speedup (and just generally be cleaner)
>
> I think I'm trying to take a stab at this

I started looking at this, but I'm not sure it makes sense to do without also changing quite a bit of other infrastructure to work on regunits at the same time



================
Comment at: llvm/lib/CodeGen/TargetRegisterInfo.cpp:270
   // Mask out the reserved registers
   BitVector Reserved = getReservedRegs(MF);
   Allocatable &= Reserved.flip();
----------------
Why is this recomputing the reserved regs instead of just querying MRI::getReservedRegs?


================
Comment at: llvm/lib/CodeGen/TargetRegisterInfo.cpp:276
 
+SmallVector<BitVector> TargetRegisterInfo::getAllocatableSets(
+    const MachineFunction &MF,
----------------
This is a separate patch


================
Comment at: llvm/lib/CodeGen/TargetRegisterInfo.cpp:280-289
+  BitVector NotReserved = getReservedRegs(MF).flip();
+  for (const TargetRegisterClass *RC : RCs) {
+    BitVector &Allocatable = AllocatableSets.emplace_back(getNumRegs());
+    // A register class with no allocatable subclass returns an empty set.
+    const TargetRegisterClass *SubClass = getAllocatableClass(RC);
+    if (SubClass)
+      getAllocatableSetForRC(MF, SubClass, Allocatable);
----------------
Most of this function is a duplictae of getAllocatableSet


Repository:
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https://reviews.llvm.org/D101939