[llvm] 5b1610a - [X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2021-05-07T20:11:20+03:00
New Revision: 5b1610a25054b308d02be8882dd34bed3dc29ef4

URL: https://github.com/llvm/llvm-project/commit/5b1610a25054b308d02be8882dd34bed3dc29ef4
DIFF: https://github.com/llvm/llvm-project/commit/5b1610a25054b308d02be8882dd34bed3dc29ef4.diff

LOG: [X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move

It measures as such, and the reference docs agree.

I can't easily add a MCA test, because there's no mnemonic for it,
it can only be disassembled or created as a MCInst.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver3.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index e0ee4dadcb60..21a9897baf2d 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -1466,7 +1466,7 @@ def : IsOptimizableRegisterMove<[
     // GPR variants.
     MOV32rr, MOV32rr_REV,
     MOV64rr, MOV64rr_REV,
-    // FIXME: MOVSXD32rr, but it is only supported in disassembler.
+    MOVSX32rr32,
     // FIXME: XCHG32rr/XCHG64rr after MCA is fixed
 
     // MMX variants.