[PATCH] D101938: [RISCV] Initial version of a demand based vsetvli insertion pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 343707.
craig.topper added a comment.

Don't add VL implicit use if VL isn't used.
Add VL implicit use to X0, X0 vsetvli.
Add experimental-v flag to addi-scalable-offset.mir


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101938/new/

https://reviews.llvm.org/D101938

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
  llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir
  llvm/test/CodeGen/RISCV/rvv/cleanup-vsetvli.mir
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir

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