[PATCH] D102074: [SLP] restrict matching of load combine candidates

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 7 08:13:19 PDT 2021


spatel created this revision.
spatel added reviewers: RKSimon, ABataev, SjoerdMeijer.
Herald added subscribers: hiraditya, mcrosier.
spatel requested review of this revision.
Herald added a project: LLVM.

The test example from https://llvm.org/PR50256 (and reduced here) shows that we can match a load combine candidate even when there are no "or" instructions. We can avoid that by confirming that we do see an "or". This doesn't apply when matching an or-reduction because that match begins from the operands of the reduction.


https://reviews.llvm.org/D102074

Files:
  llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
  llvm/test/Transforms/SLPVectorizer/AArch64/widen.ll

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