[PATCH] D101819: [DRAFT][M68k GlobaliSel]Added initial boilerplate for Call Lowering

[Shivam Gupta via Phabricator via llvm-commits]

xgupta added a comment.

In D101819#2739005 <https://reviews.llvm.org/D101819#2739005>, @sushmaunnibhavi wrote:

> @myhsu
>
> While implementing RegBankInfo for M68k, since it has 3 register classes .ie. data, address and index register classes, should I define 3 register banks in the registerBanks.td file?

@sushmaunnibhavi For this patch, I think you only care about the general-purpose register bank. Have you looked at RISCV:https://reviews.llvm.org/D65219 , PowerPC:https://reviews.llvm.org/D83100 or Mips: https://reviews.llvm.org/D43583 implementations and read the https://llvm.org/docs/GlobalISel/GMIR.html#register-bank.

Please try to start with a test case and minimal implementation to support it as described in `Head First into GlobalISel` Tutorial.

(I wish you have something before 10-12 May to commit.)


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