[PATCH] D102019: [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Limited to splats because we would need to truncate the shift
amount vector otherwise.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102019

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

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